ssp: fix the RX FIFO flushing logic

[keyonjie]

To make sure all the RX FIFO entries are read out for the flushing, we
need wait until the SSSR_RNE is cleared after the SSP is disabled (the
SSSR_BSY is cleared, otherwise, there might be obsoleted entry remained
in the FIFO which will impact the next run with the SSP RX and lead to
sample mismatched issue.

BugLink: #3428
Cc: Bartosz Kokoszko bartoszx.kokoszko@linux.intel.com
Signed-off-by: Keyon Jie yang.jie@linux.intel.com

[paulstelian97]

I'm gonna have to make similar fixes on NXP DAIs, so guess I'll take this as inspiration...

[plbossart]

I find this code absolutely horrible. The last ssp_read doesn't seem necessary and the inner loop with no limit looks like a bug.

[keyonjie]

I find this code absolutely horrible. The last ssp_read doesn't seem necessary and the inner loop with no limit looks like a bug.

@plbossart are you mean that this 'sssr = ssp_read(dai, SSSR)' is not necessary? It was original there, what's your point here?

For the inner loop with no limit, @ktrzcinx questioned about that above and I had answered above, the Linux kernel reference is here: https://github.com/torvalds/linux/blob/a1b8638ba1320e6684aa98233c15255eb803fac7/drivers/spi/spi-pxa2xx.c#L480

[plbossart]

My point exactly:

do {
		while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
			pxa2xx_spi_read(drv_data, SSDR);
	} while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
	write_SSSR_CS(drv_data, SSSR_ROR);

Why would you need another read after the 'while'?

[keyonjie]

My point exactly:

do {
		while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
			pxa2xx_spi_read(drv_data, SSDR);
	} while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
	write_SSSR_CS(drv_data, SSSR_ROR);

Why would you need another read after the 'while'?

Oh, makes sense, let me align it to kernel one and just clear the interrupt bit blindly.

done.

[fredoh9]

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