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[BUG] [TGL] [DSM] [I2S] No feedback data captured at times after SNDRV_PCM_TRIGGER_STOP/START events on pb stream #3428
Do playback on speakers
2.Start stop Start stop Start the pb stream [This start and stop refers to SNDRV_PCM_TRIGGER_STOP/START events]
3.capture feedback data for 8 seconds
4.Start stop Start stop Start the pb stream
5.capture feedback data for 8 seconds
Repeat the above for 5 times, in one of the feedback captured file, the Voltage/current data is missing.
The result is not consistent across all the captured files
This issue can be reproduced on master as well. master uses the actual DSMcomponent.i don't have data to prove this issue can be reproduced without maxim DSM as the default smart_amp throws exception with feedback stream itself as in #3432
@RDharageswari have you tried running tools/coredumper, this will help shed light on if its related to DSM module or SOF code (it should be able to take us to the line of code) which is doing the unaligned memory read..
I can reproduce this with nocodec mode, @bkokoszx I can reproduce this with below steps:
run aplay in one terminal, e.g. 'aplay -Dhw:0,2 -f s16_le -r48000 -c2 /dev/random -vvv -i'
run arecord in another terminal, e.g. 'arecord -Dhw:0,2 -f s16_le -r48000 -c2 tmp.wav -vvv'. you should see the arecord level same with aplay (e.g. aplay terminal is 99, so is the arecord terminal).
stop the arecord, and restart it, check if arecord level still correct.
do step 3 several times, you will see sometimes the arecord level is 0, which means the capture/feedback data are 0s.
@keyonjie@RDharageswari@lgirdwood
I can reproduce issue on my RVP nocodec platform with smart amplifier test component. I can see that copying process looks fine - I mean capture pipeline (even in case when arecord level is 0) processes the right amount of data. I suspect that the data is equal to 0 - I think that maybe there is some more generic problem with SSP. I will debug it.
Thanks @bkokoszx. Can you also check the PCM_START & PCM_STOP sequence once, to confirm if it is the same issue.
This is a VIVI sequence, with maxim DSM module. But you can repro on smart_amp_test component also i believe.
Activity
RDharageswari commentedon Sep 18, 2020
unable to provide more information due to this: #3432
lgirdwood commentedon Sep 18, 2020
@RDharageswari can you confirm if the exception is also on master ? Is this with real/test DSM ?
RDharageswari commentedon Sep 18, 2020
This issue can be reproduced on master as well. master uses the actual DSMcomponent.i don't have data to prove this issue can be reproduced without maxim DSM as the default smart_amp throws exception with feedback stream itself as in #3432
lgirdwood commentedon Sep 18, 2020
@RDharageswari have you tried running tools/coredumper, this will help shed light on if its related to DSM module or SOF code (it should be able to take us to the line of code) which is doing the unaligned memory read..
keyonjie commentedon Sep 23, 2020
I can reproduce this with nocodec mode, @bkokoszx I can reproduce this with below steps:
bkokoszx commentedon Sep 24, 2020
@keyonjie @RDharageswari @lgirdwood
I can reproduce issue on my RVP nocodec platform with smart amplifier test component. I can see that copying process looks fine - I mean capture pipeline (even in case when arecord level is 0) processes the right amount of data. I suspect that the data is equal to 0 - I think that maybe there is some more generic problem with SSP. I will debug it.
lgirdwood commentedon Sep 24, 2020
@bkokoszx thanks, I think we will miss v1.6- rc1 but we can hit rc final for this one.
RDharageswari commentedon Sep 24, 2020
Thanks @bkokoszx. Can you also check the PCM_START & PCM_STOP sequence once, to confirm if it is the same issue.

This is a VIVI sequence, with maxim DSM module. But you can repro on smart_amp_test component also i believe.
3 remaining items
keyonjie commentedon Sep 27, 2020
Thanks for debugging and verification, @bkokoszx and @RDharageswari .
I create a PR #3476 to fix this, please help to review.
ssp: fix the RX FIFO flushing logic
ssp: fix the RX FIFO flushing logic
ssp: fix the RX FIFO flushing logic
ssp: fix the RX FIFO flushing logic
ssp: fix the RX FIFO flushing logic
ssp: fix the RX FIFO flushing logic
keyonjie commentedon Oct 12, 2020
@RDharageswari shall we close this now?
ssp: fix the RX FIFO flushing logic