Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
Typical project for Synopsys DC Compiler
An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.
Timing path visualization.
Its Prime Time! | It is a game based on your knowledge about prime numbers. Let's see how much you know about prime numbers.
A small stupid program I wrote ages ago to find the prime numbers my military time clock shows.
数字后端设计专家 / Digital IC Physical Design Expert：12年+ 28nm–7nm 流片经验的 WorkBuddy 专家包。Netlist→GDS 实战问答：Floorplan、Placement/CTS、Routing 拥塞、STA setup/hold 收敛与 ECO、DRC/LVS、IR-drop/EM、UPF 低功耗；Innovus/ICC2/PrimeTime/Calibre/Voltus Tcl 命令与报错排查。
512-bit multi-channel DMA for shared links with channel-aware admission, hybrid buffering, CDC backends and FPGA/ASIC evidence.
Bit-exact streaming lossless codec for OFDM/radar tensors with AXI-Stream, Multi-Engine scaling, FPGA OOC and ASIC STA evidence.
Assignment of the Synthesis and Optimization of Digital Systems course of the master degree in Embedded System (Electronic Engineering) of Politecnico di Torino, academic year 2017/2018.
TCL flow for post-synthesis leakage power minimization using multi-threshold cell libraries (LVT, SVT, HVT).
ASIC synthesis and power optimisation of a SipHash core on 65 nm with Synopsys Design Compiler and PrimeTime: baseline, clock gating and multi-VT flows compared on measured PPA, plus a custom PrimeTime TCL reporter that ranks critical paths by cumulative cell power. −78 % dynamic and −52 % leakage against the baseline.
This project provides a TCL command for PrimeTime, enabling a straightforward implementation of a post-synthesis leakage power minimization procedure. Developed as part of a contest project for the course "Synthesis and Optimization of Digital Circuits" at Politecnico di Torino. This tool is designed to streamline power optimization efforts.
Complete ASIC implementation of the OpenCores DES core using Cadence Genus, Innovus, and Synopsys PrimeTime, from RTL synthesis to GDSII.
Low-Power Configurable Multi-Clock Digital System | RTL to Signoff
A lightweight local model runner for detecting issues in transcripts and conversations.
AES-128 hardware Trojan insertion and detection using power analysis (DC, VCS, PrimeTime, PrimePower).
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