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Merged
lgirdwood merged 4 commits into from
Jul 12, 2022
Merged

topology1: add support for HP Omen 16 #5974

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4d212e3
topology1: sof-tgl-rt711-rt1308: make amplifier link configuration
plbossart Jun 30, 2022
b813bc2
topology1: CMakeLists: add topology for HP Omen 16
plbossart Jul 11, 2022
0a9b092
topology1: sof-tgl-rt711-rt1308: make BT_OFFLOAD a CMakeFiles parameter
plbossart Jul 5, 2022
282076c
topology1: sof-tgl-rt711-rt1308: use EXT_AMP_REF for rt1316
plbossart Jul 5, 2022
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5 changes: 3 additions & 2 deletions tools/topology/topology1/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -129,8 +129,9 @@ set(TPLGS
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-rt1308-2ch\;-DCHANNELS=2\;-DEXT_AMP\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-rt1308-4ch\;-DCHANNELS=4\;-DEXT_AMP\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-4ch\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711-4ch\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711\;-DCHANNELS=0\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711-4ch\;-DCHANNELS=4\;-DBT_OFFLOAD\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711\;-DCHANNELS=0\;-DBT_OFFLOAD\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711-l0-rt1316-l3-2ch\;-DCHANNELS=2\;-DEXT_AMP\;-DEXT_AMP_REF\;-DAMP_1_LINK=3\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=adl"
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Outdated
## end SoundWire topologies

## SoundWire NOJACK topologies
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5 changes: 3 additions & 2 deletions tools/topology/topology1/kernel_dependent/v5.19/CMakeLists.txt
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Expand Up @@ -37,8 +37,9 @@ set(TPLGS_UP
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-rt1308-2ch\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=2\;-DEXT_AMP\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-rt1308-4ch\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=4\;-DEXT_AMP\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-tgl-rt711-4ch\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=tgl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711-4ch\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=0\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711-4ch\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=4\;-DBT_OFFLOAD\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=0\;-DBT_OFFLOAD\;-DPLATFORM=adl"
"sof-tgl-rt711-rt1308\;sof-adl-rt711-l0-rt1316-l3-2ch\;-DHEADSET_DEEP_BUFFER\;-DDYNAMIC=1\;-DCHANNELS=2\;-DEXT_AMP\;-DEXT_AMP_REF\;-DAMP_1_LINK=3\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DPLATFORM=adl"
## end SoundWire topologies
)

Expand Down
26 changes: 12 additions & 14 deletions tools/topology/topology1/sof-tgl-rt711-rt1308.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,8 @@ define(JACK_OFFSET, `0')
define(JACK_OFFSET, `2')
')

ifdef(`AMP_1_LINK',`',
`define(AMP_1_LINK, `1')')

# if there is an external RT1308 amplifier connected over SoundWire,
# enable "EXT_AMP" option in the CMakefile.
Expand Down Expand Up @@ -74,12 +76,7 @@ define(DMIC_OFFSET, `2')

define(HDMI_BE_ID_BASE, eval(JACK_OFFSET+AMP_OFFSET+AMP_REF_OFFSET+DMIC_OFFSET))

# Add Bluetooth Audio Offload pass-through for ADL
ifelse(PLATFORM, `adl',
`
define(BT_OFFLOAD)
'
)
# Add Bluetooth Audio Offload pass-through

ifdef(`BT_OFFLOAD',
` define(`BT_PIPELINE_PB_ID', `13')
Expand All @@ -100,17 +97,18 @@ DEBUG_START
# PCM31 ---> volume ------^
# PCM1 <--- volume <---- ALH 3 BE dailink 1
ifdef(`EXT_AMP', `
# PCM2 ---> volume ----> ALH 2 BE dailink 2
# PCM2 ---> volume ----> ALH 2 BE dailink AMP_1_LINK
')
# PCM5 ---> volume <---- iDisp1
# PCM6 ---> volume <---- iDisp2
# PCM7 ---> volume <---- iDisp3
# PCM8 ---> volume <---- iDisp4
# PCM10 <----volume <---- DMIC01
# PCM11 <----volume <---- DMIC16k
ifelse(PLATFORM, `adl', `
ifdef(`BT_OFFLOAD',
`
# PCM14 <---> passthrough <---> SSP2 BT playback/capture
', `')
')

# Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline with priority 0 on core 0
Expand Down Expand Up @@ -219,10 +217,10 @@ ifdef(`HEADSET_DEEP_BUFFER',

ifdef(`EXT_AMP',
`
# playback DAI is ALH(SDW1 PIN2) using 2 periods
# playback DAI is ALH(AMP_1_LINK PIN2) using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
3, ALH, 0x102, SDW1-Playback,
3, ALH, eval(AMP_1_LINK * 256 + 2), `SDW'eval(AMP_1_LINK)`-Playback',
PIPELINE_SOURCE_3, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
')
Expand Down Expand Up @@ -287,9 +285,9 @@ DAI_CONFIG(ALH, 3, 1, SDW0-Capture,

ifdef(`EXT_AMP',
`
#ALH SDW1 Pin2 (ID: 2)
DAI_CONFIG(ALH, 0x102, 2, SDW1-Playback,
ALH_CONFIG(ALH_CONFIG_DATA(ALH, 0x102, 48000, 2)))
#ALH SDW AMP_1_LINK Pin2 (ID: 2)
DAI_CONFIG(ALH, eval(AMP_1_LINK * 256 + 2), 2, `SDW'eval(AMP_1_LINK)`-Playback',
ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(AMP_1_LINK * 256 + 2), 48000, 2)))
')

# 3 HDMI/DP outputs
Expand Down