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drivers: Intel: hda-dma: Poll with timeout for DMA idle #4931

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drivers: Intel: hda-dma: Poll with timeout for DMA idle #4931

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17 changes: 12 additions & 5 deletions src/drivers/intel/hda/hda-dma.c
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include <sof/lib/dma.h>
#include <sof/lib/pm_runtime.h>
#include <sof/lib/notifier.h>
#include <sof/lib/wait.h>
#include <sof/platform.h>
#include <sof/schedule/schedule.h>
#include <sof/spinlock.h>
Expand Down Expand Up @@ -147,6 +148,9 @@ DECLARE_TR_CTX(hdma_tr, SOF_UUID(hda_dma_uuid), LOG_LEVEL_INFO);
/* DMA host transfer timeout in microseconds */
#define HDA_DMA_TIMEOUT 200

/* DMA idle timeout in microseconds */
#define HDA_DMA_IDLE_TIMEOUT_US 50

/* DMA number of buffer periods */
#define HDA_DMA_BUFFER_PERIOD_COUNT 2

Expand Down Expand Up @@ -646,7 +650,8 @@ static int hda_dma_release(struct dma_chan_data *channel)
static int hda_dma_stop_common(struct dma_chan_data *channel)
{
struct hda_chan_data *hda_chan;
uint32_t flags, dgcs;
uint32_t flags;
int ret;

irq_local_disable(flags);

Expand All @@ -667,14 +672,16 @@ static int hda_dma_stop_common(struct dma_chan_data *channel)
dma_chan_reg_update_bits(channel, DGCS, DGCS_GEN, 0);
}

/* check if channel is idle. No need to wait after clearing the GEN bit */
dgcs = dma_chan_reg_read(channel, DGCS);
if (dgcs & DGCS_GBUSY) {
/* check with timeout if channel is idle */
ret = poll_for_register_delay(dma_chan_base(channel->dma, channel->index) + DGCS,
DGCS_GBUSY, 0, HDA_DMA_IDLE_TIMEOUT_US);
if (ret < 0) {
tr_err(&hdma_tr, "hda-dmac: %d channel %d not idle after stop",
channel->dma->plat_data.id, channel->index);
irq_local_enable(flags);
return -EBUSY;
return ret;
}

@plbossart plbossart Oct 27, 2021

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the addition of a wait seems ok, but this is done in code where interrupts are disabled. Isn't that creating a bigger problem?

@ranj063 ranj063 Oct 27, 2021

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that is a good point but we have a similar polling with interrutps disabled in

sof/src/drivers/dw/dma.c

Line 423 in 215b13f

ret = poll_for_register_delay(dma_base(dma) +

Not sayng that code is right, just saying that we have precedence for doing something similar

@lgirdwood lgirdwood Oct 29, 2021

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@ranj063 this change will be fine with @lyakh trigger STOP update. We will also need to make sure it works with DW DMA as above. @lyakh fyi it looks like DW DMA has a 1.5ms poll delay which may mean we need to have a delayed stop (like early BCLK) where we use the LL scheduler ticks to wait on the DW DMA event.

channel->status = COMP_STATE_PREPARE;
hda_chan = dma_chan_get_data(channel);
hda_chan->state = 0;
Expand Down