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Poll the DGCS register with a timeout to check if the DMA is idle after clearing the GEN bit. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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the addition of a wait seems ok, but this is done in code where interrupts are disabled. Isn't that creating a bigger problem?
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that is a good point but we have a similar polling with interrutps disabled in
Line 423 in 215b13f
Not sayng that code is right, just saying that we have precedence for doing something similar
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@ranj063 this change will be fine with @lyakh trigger STOP update. We will also need to make sure it works with DW DMA as above. @lyakh fyi it looks like DW DMA has a 1.5ms poll delay which may mean we need to have a delayed stop (like early BCLK) where we use the LL scheduler ticks to wait on the DW DMA event.
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Environment without this commit , it happened (not sure which round) |
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Is this PR still relevant @ranj063 ? |
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Poll the DGCS register with a timeout to check if the DMA is idle after
clearing the GEN bit.
potential fix for #4919