Refine wait functions

src/include/sof/wait.h

@@ -166,7 +166,8 @@ static inline void wait_delay(uint64_t number_of_clks)
 
 static inline int poll_for_completion_delay(completion_t *comp, uint64_t us)
 {
-	uint64_t tick = clock_ms_to_ticks(CLK_CPU, 1) * us / 1000;
+	uint64_t tick = clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) *
+						us / 1000;
 	uint32_t tries = DEFAULT_TRY_TIMES;
 	uint64_t delta = tick / tries;
 
@@ -191,7 +192,8 @@ static inline int poll_for_register_delay(uint32_t reg,
 					  uint32_t mask,
 					  uint32_t val, uint64_t us)
 {
-	uint64_t tick = clock_ms_to_ticks(CLK_CPU, 1) * us / 1000;
+	uint64_t tick = clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) *
+						us / 1000;
 	uint32_t tries = DEFAULT_TRY_TIMES;
 	uint64_t delta = tick / tries;
 

src/ipc/pmc-ipc.c

@@ -126,7 +126,7 @@ static void irq_handler(void *arg)
 int ipc_pmc_send_msg(uint32_t message)
 {
 	uint32_t ipclpesch;
-	int try = 0;
+	int ret;
 
 	trace_ipc("SMs");
 
@@ -142,21 +142,13 @@ int ipc_pmc_send_msg(uint32_t message)
 	shim_write(SHIM_IPCLPESCL, 0);
 	shim_write(SHIM_IPCLPESCH, SHIM_IPCLPESCH_BUSY | message);
 
-	/* check status */
-	ipclpesch = shim_read(SHIM_IPCLPESCH);
-
-	while (ipclpesch & SHIM_IPCLPESCH_BUSY) {
-		/* now wait for clock change */
-		idelay(PLATFORM_LPE_DELAY);
-		ipclpesch = shim_read(SHIM_IPCLPESCH);
-
-		try++;
-		if (try > 10)
-			break;
-	}
+	/* wait for idle status */
+	ret = poll_for_register_delay(SHIM_BASE + SHIM_IPCLPESCH,
+				      SHIM_IPCLPESCH_BUSY, 0,
+				      PLATFORM_LPE_DELAY);
 
 	/* did command succeed */
-	if (ipclpesch & SHIM_IPCLPESCH_BUSY) {
+	if (ret < 0) {
 		trace_ipc_error("ePf");
 		return -EINVAL;
 	}

src/platform/apollolake/include/platform/platform.h

@@ -41,6 +41,15 @@
 
 struct sof;
 
+/*! \def PLATFORM_DEFAULT_CLOCK
+ *  \brief clock source for audio pipeline
+ *
+ *  There are two types of clock: cpu clock which is a internal clock in
+ *  xtensa core, and ssp clock which is provided by external HW IP.
+ *  The choice depends on HW features on different platform
+ */
+#define PLATFORM_DEFAULT_CLOCK CLK_SSP
+
 /* DGMBS align value */
 #define PLATFORM_HDA_BUFFER_ALIGNMENT	0x20
 
@@ -74,7 +83,7 @@ struct sof;
 #define PLATFORM_MAX_STREAMS	16
 
 /* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK	CLK_SSP
+#define PLATFORM_SCHED_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
 #define PLATFORM_DMA_TIMEOUT	1333
@@ -86,7 +95,7 @@ struct sof;
 #define PLATFORM_WORKQ_WINDOW	2000
 
 /* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK	CLK_SSP
+#define PLATFORM_WORKQ_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* Host finish work schedule delay in microseconds */
 #define PLATFORM_HOST_FINISH_DELAY	100

src/platform/baytrail/include/platform/platform.h

@@ -40,6 +40,15 @@
 
 struct sof;
 
+/*! \def PLATFORM_DEFAULT_CLOCK
+ *  \brief clock source for audio pipeline
+ *
+ *  There are two types of clock: cpu clock which is a internal clock in
+ *  xtensa core, and ssp clock which is provided by external HW IP.
+ *  The choice depends on HW features on different platform
+ */
+#define PLATFORM_DEFAULT_CLOCK CLK_SSP
+
 /* IPC Interrupt */
 #define PLATFORM_IPC_INTERRUPT	IRQ_NUM_EXT_IA
 
@@ -67,7 +76,7 @@ struct sof;
 #define PLATFORM_MAX_STREAMS	5
 
 /* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK	CLK_SSP
+#define PLATFORM_SCHED_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
 #define PLATFORM_DMA_TIMEOUT	1333
@@ -79,7 +88,7 @@ struct sof;
 #define PLATFORM_WORKQ_WINDOW	2000
 
 /* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK	CLK_SSP
+#define PLATFORM_WORKQ_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* local buffer size of DMA tracing */
 #define DMA_TRACE_LOCAL_SIZE	HOST_PAGE_SIZE

src/platform/cannonlake/include/platform/platform.h

@@ -42,6 +42,15 @@
 
 struct sof;
 
+/*! \def PLATFORM_DEFAULT_CLOCK
+ *  \brief clock source for audio pipeline
+ *
+ *  There are two types of clock: cpu clock which is a internal clock in
+ *  xtensa core, and ssp clock which is provided by external HW IP.
+ *  The choice depends on HW features on different platform
+ */
+#define PLATFORM_DEFAULT_CLOCK CLK_SSP
+
 #define PLATFORM_WAITI_DELAY	1
 
 #define PLATFORM_SSP_COUNT 3
@@ -80,7 +89,7 @@ struct sof;
 #define PLATFORM_MAX_STREAMS	5
 
 /* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK	CLK_SSP
+#define PLATFORM_SCHED_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
 #define PLATFORM_DMA_TIMEOUT	1333
@@ -92,7 +101,7 @@ struct sof;
 #define PLATFORM_WORKQ_WINDOW	2000
 
 /* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK	CLK_SSP
+#define PLATFORM_WORKQ_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* Host finish work schedule delay in microseconds */
 #define PLATFORM_HOST_FINISH_DELAY	100

src/platform/haswell/include/platform/platform.h

@@ -39,6 +39,15 @@
 
 struct sof;
 
+/*! \def PLATFORM_DEFAULT_CLOCK
+ *  \brief clock source for audio pipeline
+ *
+ *  There are two types of clock: cpu clock which is a internal clock in
+ *  xtensa core, and ssp clock which is provided by external HW IP.
+ *  The choice depends on HW features on different platform
+ */
+#define PLATFORM_DEFAULT_CLOCK CLK_CPU
+
 /* IPC Interrupt */
 #define PLATFORM_IPC_INTERRUPT	IRQ_NUM_EXT_IA
 
@@ -66,7 +75,7 @@ struct sof;
 #define PLATFORM_MAX_STREAMS	5
 
 /* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK	CLK_CPU
+#define PLATFORM_SCHED_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
 #define PLATFORM_DMA_TIMEOUT	1333
@@ -78,7 +87,7 @@ struct sof;
 #define PLATFORM_WORKQ_WINDOW	2000
 
 /* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK	CLK_CPU
+#define PLATFORM_WORKQ_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* local buffer size of DMA tracing */
 #define DMA_TRACE_LOCAL_SIZE	HOST_PAGE_SIZE

src/platform/icelake/include/platform/platform.h

@@ -42,6 +42,15 @@
 
 struct sof;
 
+/*! \def PLATFORM_DEFAULT_CLOCK
+ *  \brief clock source for audio pipeline
+ *
+ *  There are two types of clock: cpu clock which is a internal clock in
+ *  xtensa core, and ssp clock which is provided by external HW IP.
+ *  The choice depends on HW features on different platform
+ */
+#define PLATFORM_DEFAULT_CLOCK CLK_SSP
+
 #define PLATFORM_WAITI_DELAY	1
 
 #define PLATFORM_SSP_COUNT 3
@@ -80,7 +89,7 @@ struct sof;
 #define PLATFORM_MAX_STREAMS	5
 
 /* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK	CLK_SSP
+#define PLATFORM_SCHED_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
 #define PLATFORM_DMA_TIMEOUT	1333
@@ -92,7 +101,7 @@ struct sof;
 #define PLATFORM_WORKQ_WINDOW	2000
 
 /* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK	CLK_SSP
+#define PLATFORM_WORKQ_CLOCK	PLATFORM_DEFAULT_CLOCK
 
 /* Host finish work schedule delay in microseconds */
 #define PLATFORM_HOST_FINISH_DELAY	100