platform: refactor: move clock, interrupt and timer to drivers

configure.ac

@@ -454,11 +454,16 @@ AC_CONFIG_FILES([
 	src/audio/Makefile
 	src/math/Makefile
 	src/drivers/Makefile
+	src/drivers/intel/Makefile
+	src/drivers/intel/baytrail/Makefile
+	src/drivers/intel/haswell/Makefile
+	src/drivers/intel/cavs/Makefile
 	src/include/Makefile
 	src/include/sof/Makefile
 	src/include/sof/audio/Makefile
 	src/include/sof/audio/coefficients/Makefile
 	src/include/sof/audio/coefficients/src/Makefile
+	src/include/sof/drivers/Makefile
 	src/include/sof/math/Makefile
 	src/include/uapi/Makefile
 	src/ipc/Makefile

src/arch/xtensa/Makefile.am

@@ -94,7 +94,7 @@ sof_LDADD = \
 	../../ipc/libsof_ipc.a \
 	../../lib/libdma.a \
 	../../audio/libaudio.a \
-	../../drivers/libdrivers.a \
+	../../drivers/libdrivers.la \
 	../../math/libsof_math.a \
 	-lgcc
 

src/drivers/Makefile.am

@@ -1,47 +1,15 @@
-noinst_LIBRARIES = libdrivers.a
+SUBDIRS = intel
 
-libdrivers_a_SOURCES = \
-	dw-dma.c
+noinst_LTLIBRARIES = libdrivers.la
 
-if BUILD_BAYTRAIL
-libdrivers_a_SOURCES += \
-	byt-ssp.c
-endif
-
-if BUILD_CHERRYTRAIL
-libdrivers_a_SOURCES += \
-	byt-ssp.c
-endif
-
-if BUILD_HASWELL
-libdrivers_a_SOURCES += \
-	hsw-ssp.c
-endif
-
-if BUILD_BROADWELL
-libdrivers_a_SOURCES += \
-	hsw-ssp.c
-endif
-
-if BUILD_APOLLOLAKE
-libdrivers_a_SOURCES += \
-	apl-ssp.c \
-	hda-dma.c \
-	cavs-hda.c \
-	dmic.c
-endif
-
-if BUILD_CANNONLAKE
-libdrivers_a_SOURCES += \
-	apl-ssp.c \
-	hda-dma.c \
-	cavs-hda.c \
-	dmic.c
-endif
-
-libdrivers_a_CFLAGS = \
+libdrivers_la_CFLAGS = \
 	$(AM_CFLAGS) \
 	$(ARCH_CFLAGS) \
 	$(PLATFORM_INCDIR) \
 	$(SOF_INCDIR) \
 	$(ARCH_INCDIR)
+
+# This lib is just composition of convenience libraries
+libdrivers_la_SOURCES =
+
+libdrivers_la_LIBADD = intel/libdrivers.la

src/drivers/intel/Makefile.am

@@ -0,0 +1,39 @@
+noinst_LTLIBRARIES = libdrivers.la
+
+libdrivers_la_CFLAGS = \
+	$(AM_CFLAGS) \
+	$(ARCH_CFLAGS) \
+	$(PLATFORM_INCDIR) \
+	$(SOF_INCDIR) \
+	$(ARCH_INCDIR)
+
+libdrivers_la_SOURCES = dw-dma.c
+
+if BUILD_CAVS
+
+SUBDIRS = cavs
+libdrivers_la_LIBADD = cavs/libdrivers.la
+
+else
+
+if BUILD_BAYTRAIL
+SUBDIRS = baytrail
+libdrivers_la_LIBADD = baytrail/libdrivers.la
+endif
+
+if BUILD_CHERRYTRAIL
+SUBDIRS = baytrail
+libdrivers_la_LIBADD = baytrail/libdrivers.la
+endif
+
+if BUILD_HASWELL
+SUBDIRS = haswell
+libdrivers_la_LIBADD = haswell/libdrivers.la
+endif
+
+if BUILD_BROADWELL
+SUBDIRS = haswell
+libdrivers_la_LIBADD = haswell/libdrivers.la
+endif
+
+endif

src/drivers/intel/baytrail/Makefile.am

@@ -0,0 +1,14 @@
+noinst_LTLIBRARIES = libdrivers.la
+
+libdrivers_la_SOURCES = \
+	clk.c \
+	interrupt.c \
+	ssp.c \
+	timer.c
+
+libdrivers_la_CFLAGS = \
+	$(AM_CFLAGS) \
+	$(ARCH_CFLAGS) \
+	$(PLATFORM_INCDIR) \
+	$(SOF_INCDIR) \
+	$(ARCH_INCDIR)

src/platform/baytrail/clk.c → src/drivers/intel/baytrail/clk.c

@@ -29,6 +29,7 @@
  *         Keyon Jie <yang.jie@linux.intel.com>
  */
 
+#include <sof/drivers/clk.h>
 #include <sof/clock.h>
 #include <sof/io.h>
 #include <sof/sof.h>
@@ -49,6 +50,8 @@
 struct clk_data {
 	uint32_t freq;
 	uint32_t ticks_per_usec;
+
+	/* for synchronizing freq set for each clock */
 	spinlock_t lock;
 };
 
@@ -111,10 +114,8 @@ static const struct freq_table ssp_freq[] = {
 #error No target defined
 #endif
 
-
-
 static inline uint32_t get_freq(const struct freq_table *table, int size,
-	unsigned int hz)
+				unsigned int hz)
 {
 	uint32_t i;
 
@@ -172,16 +173,15 @@ uint32_t clock_set_freq(int clock, uint32_t hz)
 
 		/* tell anyone interested we are about to change CPU freq */
 		notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_PRE,
-			&notify_data);
+			       &notify_data);
 
 		/* set CPU frequency request for CCU */
 		io_reg_update_bits(SHIM_BASE + SHIM_FR_LAT_REQ,
-				SHIM_FR_LAT_CLK_MASK, cpu_freq[idx].enc);
+				   SHIM_FR_LAT_CLK_MASK, cpu_freq[idx].enc);
 
 		/* send freq request to SC */
 		err = ipc_pmc_send_msg(PMC_SET_LPECLK);
 		if (err == 0) {
-
 			/* update clock frequency */
 			clk_pdata->clk[clock].freq = cpu_freq[idx].freq;
 			clk_pdata->clk[clock].ticks_per_usec =
@@ -190,7 +190,7 @@ uint32_t clock_set_freq(int clock, uint32_t hz)
 
 		/* tell anyone interested we have now changed CPU freq */
 		notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_POST,
-			&notify_data);
+			       &notify_data);
 		break;
 	case CLK_SSP:
 		/* get nearest frequency that is >= requested Hz */
@@ -199,12 +199,11 @@ uint32_t clock_set_freq(int clock, uint32_t hz)
 
 		/* tell anyone interested we are about to change CPU freq */
 		notifier_event(NOTIFIER_ID_SSP_FREQ, CLOCK_NOTIFY_PRE,
-			&notify_data);
+			       &notify_data);
 
 		/* send SSP freq request to SC */
 		err = ipc_pmc_send_msg(ssp_freq[idx].enc);
 		if (err == 0) {
-
 			/* update clock frequency */
 			clk_pdata->clk[clock].freq = ssp_freq[idx].freq;
 			clk_pdata->clk[clock].ticks_per_usec =
@@ -213,7 +212,7 @@ uint32_t clock_set_freq(int clock, uint32_t hz)
 
 		/* tell anyone interested we have now changed CPU freq */
 		notifier_event(NOTIFIER_ID_SSP_FREQ, CLOCK_NOTIFY_POST,
-			&notify_data);
+			       &notify_data);
 		break;
 
 	default:

src/drivers/intel/baytrail/interrupt.c

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of the Intel Corporation nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ *         Janusz Jankowski <janusz.jankowski@linux.intel.com>
+ *
+ */
+
+#include <sof/sof.h>
+#include <sof/interrupt.h>
+
+void platform_interrupt_init(void) {}
+
+struct irq_desc *platform_irq_get_parent(uint32_t irq)
+{
+	return NULL;
+}
+
+void platform_interrupt_set(int irq)
+{
+	arch_interrupt_set(irq);
+}
+
+/* clear mask in PISR, bits are W1C in docs but some bits need preserved ?? */
+void platform_interrupt_clear(uint32_t irq, uint32_t mask)
+{
+	switch (irq) {
+	case IRQ_NUM_EXT_SSP0:
+		shim_write(SHIM_PISR, mask << 3);
+		interrupt_clear(irq);
+		break;
+	case IRQ_NUM_EXT_SSP1:
+		shim_write(SHIM_PISR, mask << 4);
+		interrupt_clear(irq);
+		break;
+	case IRQ_NUM_EXT_SSP2:
+		shim_write(SHIM_PISR, mask << 5);
+		interrupt_clear(irq);
+		break;
+	case IRQ_NUM_EXT_DMAC0:
+		shim_write(SHIM_PISR, mask << 16);
+		interrupt_clear(irq);
+		break;
+	case IRQ_NUM_EXT_DMAC1:
+		shim_write(SHIM_PISR, mask << 24);
+		interrupt_clear(irq);
+		break;
+#if defined CONFIG_CHERRYTRAIL
+	case IRQ_NUM_EXT_DMAC2:
+		shim_write(SHIM_PISRH, mask << 0);
+		interrupt_clear(irq);
+		break;
+	case IRQ_NUM_EXT_SSP3:
+		shim_write(SHIM_PISRH, mask << 8);
+		interrupt_clear(irq);
+		break;
+	case IRQ_NUM_EXT_SSP4:
+		shim_write(SHIM_PISRH, mask << 9);
+		interrupt_clear(irq);
+		break;
+	case IRQ_NUM_EXT_SSP5:
+		shim_write(SHIM_PISRH, mask << 10);
+		interrupt_clear(irq);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+/* TODO: expand this to 64 bit - should we just return mask of IRQ numbers */
+uint32_t platform_interrupt_get_enabled(void)
+{
+	return shim_read(SHIM_PIMR);
+}
+
+void platform_interrupt_mask(uint32_t irq, uint32_t mask)
+{
+	switch (irq) {
+	case IRQ_NUM_EXT_SSP0:
+		shim_write(SHIM_PIMR, mask << 3);
+		break;
+	case IRQ_NUM_EXT_SSP1:
+		shim_write(SHIM_PIMR, mask << 4);
+		break;
+	case IRQ_NUM_EXT_SSP2:
+		shim_write(SHIM_PIMR, mask << 5);
+		break;
+	case IRQ_NUM_EXT_DMAC0:
+		shim_write(SHIM_PIMR, mask << 16);
+		break;
+	case IRQ_NUM_EXT_DMAC1:
+		shim_write(SHIM_PIMR, mask << 24);
+		break;
+#if defined CONFIG_CHERRYTRAIL
+	case IRQ_NUM_EXT_DMAC2:
+		shim_write(SHIM_PIMRH, mask << 8);
+		break;
+	case IRQ_NUM_EXT_SSP3:
+		shim_write(SHIM_PIMRH, mask << 0);
+		break;
+	case IRQ_NUM_EXT_SSP4:
+		shim_write(SHIM_PIMRH, mask << 1);
+		break;
+	case IRQ_NUM_EXT_SSP5:
+		shim_write(SHIM_PIMRH, mask << 2);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
+{
+	switch (irq) {
+	case IRQ_NUM_EXT_SSP0:
+		shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 3));
+		break;
+	case IRQ_NUM_EXT_SSP1:
+		shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 4));
+		break;
+	case IRQ_NUM_EXT_SSP2:
+		shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 5));
+		break;
+	case IRQ_NUM_EXT_DMAC0:
+		shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 16));
+		break;
+	case IRQ_NUM_EXT_DMAC1:
+		shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 24));
+		break;
+#if defined CONFIG_CHERRYTRAIL
+	case IRQ_NUM_EXT_DMAC2:
+		shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 8));
+		break;
+	case IRQ_NUM_EXT_SSP3:
+		shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 0));
+		break;
+	case IRQ_NUM_EXT_SSP4:
+		shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 1));
+		break;
+	case IRQ_NUM_EXT_SSP5:
+		shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 2));
+		break;
+#endif
+	default:
+		break;
+	}
+}