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Topology: BYT: Adjust SRC pipeline for lower RAM consumption #2555

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Merged
lgirdwood merged 1 commit into from
Mar 16, 2020
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Topology: BYT: Adjust SRC pipeline for lower RAM consumption #2555

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8 changes: 4 additions & 4 deletions tools/topology/sof-byt-codec.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -56,11 +56,11 @@ DAI_ADD(sof/pipe-dai-playback.m4,
1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA)

# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le.
# 4000us deadline on core 0 with priority 0
# 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4,
3, 1, 2, s16le,
4000, 0, 0,
8000, 96000, 48000,
3, 1, 2, s32le,
1000, 0, 0,
8000, 48000, 48000,

@plbossart plbossart Mar 16, 2020

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humm, how does removing 96kHz -> 48kHz reduce RAM consumption. It's rather straightforward with a 1/2 ratio and subsampling?
Or did you mean that this included 88.2->48kHz which is indeed useless?
Wondering if the range is the problem, and if we need a discrete set of frequencies instead.

@juimonen juimonen Mar 16, 2020

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@plbossart I guess because buffering is always 1ms so 96000 -> bigger buffers after src...

@juimonen juimonen Mar 16, 2020

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before src I meant...

@singalsu singalsu Mar 16, 2020

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Yep, the macro to compute buffer sizes handles this.

SCHEDULE_TIME_DOMAIN_DMA,
PIPELINE_PLAYBACK_SCHED_COMP_1)

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16 changes: 8 additions & 8 deletions tools/topology/sof/pipe-pcm-media.m4
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Expand Up @@ -54,22 +54,22 @@ W_DATA(playback_pga_conf, playback_pga_tokens)
# with 2 sink and 0 source periods
W_PCM_PLAYBACK(PCM_ID, Media Playback, 2, 0)

# "Playback Volume" has 2 sink period and 2 source periods for host ping-pong
W_PGA(0, PIPELINE_FORMAT, 2, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID PCM PCM_ID Playback Volume"))
# "Playback Volume" has 3 sink period and 2 source periods for host ping-pong
W_PGA(0, PIPELINE_FORMAT, 3, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID PCM PCM_ID Playback Volume"))

# "SRC 0" has 2 sink and source periods.
W_SRC(0, PIPELINE_FORMAT, 2, 2, media_src_conf)
# "SRC 0" has 3 sink and source periods.
W_SRC(0, PIPELINE_FORMAT, 3, 3, media_src_conf)

@plbossart plbossart Mar 16, 2020

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comment above seems inconsistent?

@singalsu singalsu Mar 16, 2020 •
edited
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I think there was a mistake in topology originally.

There's similar for W_PGA() above but I didn't change it yet. It could be 3, 3 since the buffers are anyway allocated such way. Maybe I should change it too?

@lgirdwood lgirdwood Mar 16, 2020

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yep, please change comment.

@singalsu singalsu Mar 16, 2020

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It's fixed now. I also changed B0 to 2 periods, no need for 3, and changed for volume component sink to 3 periods to match B1.


# Media Source Buffers to SRC, make them big enough to deal with 2 * rate.
W_BUFFER(0, COMP_BUFFER_SIZE(4,
# Media Source Buffers to SRC
W_BUFFER(0, COMP_BUFFER_SIZE(2,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
PLATFORM_HOST_MEM_CAP)
W_BUFFER(1,COMP_BUFFER_SIZE(4,
W_BUFFER(1,COMP_BUFFER_SIZE(3,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
PLATFORM_COMP_MEM_CAP)

# Buffer B2 is on fixed rate sink side of SRC.
W_BUFFER(2, COMP_BUFFER_SIZE(4,
W_BUFFER(2, COMP_BUFFER_SIZE(3,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
PLATFORM_COMP_MEM_CAP)

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