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Topology: BYT: Adjust SRC pipeline for lower RAM consumption - #2555
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I assume you meant "reduced from 4 to 3" in the commit and PR description, right? |
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@paulstelian97 Yep. need to re-post this! |
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Thanks, it's fixed now! |
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comment above seems inconsistent?
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I think there was a mistake in topology originally.
There's similar for W_PGA() above but I didn't change it yet. It could be 3, 3 since the buffers are anyway allocated such way. Maybe I should change it too?
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It's fixed now. I also changed B0 to 2 periods, no need for 3, and changed for volume component sink to 3 periods to match B1.
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humm, how does removing 96kHz -> 48kHz reduce RAM consumption. It's rather straightforward with a 1/2 ratio and subsampling?
Or did you mean that this included 88.2->48kHz which is indeed useless?
Wondering if the range is the problem, and if we need a discrete set of frequencies instead.
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@plbossart I guess because buffering is always 1ms so 96000 -> bigger buffers after src...
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Yep, the macro to compute buffer sizes handles this.
This patch removes support for over 48 kHz sample rates and changes scheduling to every 1 ms to save in buffers sizes. In pipe-pcm-media.m4 the buffers in the pipeline are reduced from 4 to 2 or 3 periods. These changes should allow the media PCM to work in BYT platform. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
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This patch removes support for over 48 kHz sample rates and changes
scheduling to every 1 ms to save in buffers sizes. In pipe-pcm-media.m4
the buffers in the pipeline are reduced by one period from 4 to 3.
These changes should allow the media PCM to work in BYT platform.
Signed-off-by: Seppo Ingalsuo seppo.ingalsuo@linux.intel.com