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ll_scheduler: add check for newly calculated timeout - #1768
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On what platform have you measured it? I think it will differ for different XTAL frequencies.
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The amount of ticks should be clock frequency independant. However it is DSP and compiler dependant so I related it with compiler used. I think it should be moved to arch directory as it is valid only for xtensa ISA
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Now the question is, why do we have such situation? |
When FW is configured with more advanced, rich topologies like KWD + separate playback/capture or both then on startup and pause/suspend case we sporadically observe such issue. The reproduction rate is about 10%. To be clear 10% of cold starts or pause/suspends result in this issue, any other time we are safe. |
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More efficient to do this
temp_ticks = ll_get_timer(queue) + TICKS_NEEDED_;
if (ticks < temp_ticks)
ticks = temp_ticks;There was a problem hiding this comment.
Yes sure, there is no need to call ll_get_timer() twice.
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@mrajwa We need to add some kind of error message to notify late task processing and also we need to rootcause the reason of such behavior. Based on your description there is still no reason why timer interrupt is handled so late. |
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@tlauda, sure, I am OK with error message. However this is not the only demanding IPC request. While debugging I have stumbled upon several others which takes like 400-500 uS to accomplish. So if they happen to end up on IRQ list in series before our scheduler handler like IPC_400_uS - IPC_500_uS - TIMER_IRQ we will end up with exact same situation. Although this is much much less likely. |
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@mrajwa IPC task is executed on lower irq level than timer scheduler, so it should be automatically preempted. We should analyze if the pipeline_params method really needs to disable global interrupts. |
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@tlauda, @lgirdwood PR is updated. Can we merge now? |
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I think it will be overkill in this scenario - it's true that this value is architecture dependent (and we have it wrapped up by precompiler-architecture check) but in the same time it is dependent on scheduler implementation.
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@mrajwa it's platform/arch level config, lets put in all in one global place.
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SOFCI TEST |
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@mrajwa please split it to have irq fix and ticks workaround as separate PRs |
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@mrajwa Internal CI showing degredation in SNR for TGL ? Can you confirm the is false positive. |
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@lgirdwood interesting, where did you see that? Can you give me a reference so I can check? All tests already run passed fine (except pause/resume one but this is known issue) |
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I don't think we need to check it here. It's calculated from the current time, not last_tick.
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Yes the argument to queue_calc_next_timeout() is current time but there is no guarantee the time returned from it will not be past time
return queue->ticks_per_msec * queue->timeout / 1000 + start;
In above statement its enough somebody sets queue->timeout to incorrect value and we may have problems.
To summarise I would keep this check here.
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If it's needed then please add some comments to this effect. This way other will understand why we do the check.
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SOFCI TEST |
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The function returns int and here we can have up to 64 bit value.
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You suggest to return the 64 bit value which was set I assume. I was also thinking about that but the return of difference, or 0 if there is no diff would be aliggned better with other .set_timer() interfaces like for BYT platform for example. So the ABI is more a like. What do you think?
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@mrajwa Are we absolutely sure that the difference will fit into an "int", even in the worse cases where something will delay this code too much?
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@mrajwa @paulstelian97 This is what I was talking about. We can potentially have more than 32 bits here.
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Fair point, lets make it int64_t then.
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In this scenario I also changed the return value itself to be a value written to compare register instead of a difference between requested and set ticks. Even though int64_t max value is half of what uin64_t can offer, it is still enough.
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If it's needed then please add some comments to this effect. This way other will understand why we do the check.
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SOFCI TEST |
massive CI failures. doesn't look safe... |
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@mrajwa Conflicts. |
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@lgirdwood, updated is it OK for you now? |
It was due to conflicts in one file which happened in the meantime. |
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@mrajwa can you check and comment on the CI errors. |
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Now the two CI test case failures are known issue in firmware/driver. thanks! @mrajwa @lgirdwood |
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@mrajwa good to merge once conflicts fixed. |
This patch reworks cAVS timer_set() interface used to write into timer's compare register. This change takes care of ticks request which are "past time". If such condition occur we set compare register to current time so the latency is minimum. Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This patch checks if during scheduling we were delayed. If such situation happens we log error message. Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
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This patch checks if newly created timeout is not a
past time. Such issue will lead to dead scheduler.
NOTE! This will cause slight delay in tasks start time (only when previous tasks took more than scheduled period). I keep investigating what potential consequences it can cause, as for now it looks pretty safe.
Signed-off-by: Marcin Rajwa marcin.rajwa@linux.intel.com