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SoundWire: improve bus reset - #4225
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plbossart merged 4 commits intoApr 17, 2023
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ranj063
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plbossart
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Mar 7, 2023
It's not clear why we enabled interrupts in the Cadence IP first. The logical programming sequence should be to first start the bus, and only second to enable the interrupts. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
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Tested on TigerLake UpXtreme + 4 x CS35L56 (EIGHT-C/AIC1.0).When exiting clock stop there's some initial bus activity which is too short for the analyzer to decode, but I assume it is PINGs. Then a full bus-reset and CS35L56 audio is working. |
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Thanks @rfvirgil for testing, I'll do more testing on my end when our CI is back in gear. Happy Friday! |
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SOFCI TEST |
plbossart
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April 7, 2023 16:54
plbossart
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April 7, 2023 16:54
bardliao
previously approved these changes
Apr 10, 2023
Combining hardware reset with the multi-link mode leads to a shortened hardware reset pattern observed on the bus. The updated hardware programming sequence is to first enable the clock with the sync_arm/sync_go pattern, and only in a second step to issue the hardware reset sequence. Since there is no longer a dependency between sync_arm/sync_go and hw_reset, the behavior of sdw_cdns_exit_reset() is changed to wait for the self-clearing CONFIG_UPDATE to go back to zero, Link: thesofproject#4170 Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
We want to wait for the CONFIG_UPDATE bit to clear before doing something else. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
We use __func__ in all calls of sdw_cdns_check_self_clearing_bits(), except in one case. Likely an editing miss when the code was refactored. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
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v2 added, the main change is the addition of a wait in exit_reset diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c
index 9ca600f1fa19..eb1b87ad1681 100644
--- a/drivers/soundwire/cadence_master.c
+++ b/drivers/soundwire/cadence_master.c
@@ -456,9 +456,9 @@ static int cdns_parity_error_injection(void *data, u64 value)
CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR);
/* commit changes */
- cdns_updatel(cdns, CDNS_MCP_CONFIG_UPDATE,
- CDNS_MCP_CONFIG_UPDATE_BIT,
- CDNS_MCP_CONFIG_UPDATE_BIT);
+ ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
+ if (ret < 0)
+ goto unlock;
/* do a broadcast dummy read to avoid bus clashes */
ret = sdw_bread_no_pm_unlocked(&cdns->bus, 0xf, SDW_SCP_DEVID_0);
@@ -470,16 +470,17 @@ static int cdns_parity_error_injection(void *data, u64 value)
0);
/* commit changes */
- cdns_updatel(cdns, CDNS_MCP_CONFIG_UPDATE,
- CDNS_MCP_CONFIG_UPDATE_BIT,
- CDNS_MCP_CONFIG_UPDATE_BIT);
-
- /* Continue bus operation with parity error injection disabled */
- mutex_unlock(&bus->bus_lock);
+ ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
+ if (ret < 0)
+ goto unlock;
/* Userspace changed the hardware state behind the kernel's back */
add_taint(TAINT_USER, LOCKDEP_STILL_OK);
+unlock:
+ /* Continue bus operation with parity error injection disabled */
+ mutex_unlock(&bus->bus_lock);
+
/*
* allow Master device to enter pm_runtime suspend. This may
* also result in Slave devices suspending.
@@ -1139,13 +1140,7 @@ int sdw_cdns_exit_reset(struct sdw_cdns *cdns)
CDNS_MCP_CONTROL_HW_RST);
/* commit changes */
- cdns_updatel(cdns, CDNS_MCP_CONFIG_UPDATE,
- CDNS_MCP_CONFIG_UPDATE_BIT,
- CDNS_MCP_CONFIG_UPDATE_BIT);
-
- /* don't wait here */
- return 0;
-
+ return cdns_config_update(cdns);
}
EXPORT_SYMBOL(sdw_cdns_exit_reset);
diff --git a/drivers/soundwire/intel_bus_common.c b/drivers/soundwire/intel_bus_common.c
index be0c93106fc8..e5ac3cc7cb79 100644
--- a/drivers/soundwire/intel_bus_common.c
+++ b/drivers/soundwire/intel_bus_common.c
@@ -182,8 +182,7 @@ int intel_start_bus_after_clock_stop(struct sdw_intel *sdw)
return ret;
}
- sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks",
- true, INTEL_MASTER_RESET_ITERATIONS);
+ sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS);
return 0;
} |
bardliao
approved these changes
Apr 11, 2023
RanderWang
approved these changes
Apr 11, 2023
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Tentative PR to check CI results on multiple generations of hardware. Tested successfully with MODEL=TGLU_SKU0A32_SDCA