Seeing truncated Bus Reset exiting clock-stop on UpXtreme

On Whiskeylake and Tigerlake UpXtreme boards I am seeing that on exit from clock-stop the SoundWire Manager starts to toggle the data line for a Bus Reset but this toggling stops well before the 4096 toggles required for a Bus Reset. The Peripheral driver's unattach_request has been set, so it is expecting to have been reset.
After the truncated Bus Reset the Manager continues to issue bus transactions.

The attached screenshots are from a Saleae Logic showing one of these truncated Bus Resets on a TGL. In this case there are only around 201 toggles.

System:
UpXtreme "i11". Tigerlake. Celeron. SWIRE_CLK = 4.8 MHz
OR
UpXtreme Whiskeylake, Celeron. SWIRE_CLK = 6.0 MHz
4x CS35L56 on link 0

SOF firmware: v2.2.2

Kernel:
6.1 with some additional patches to drivers/soundwire:
b9d50eb52dfd soundwire: export sdw_nwrite_no_pm and sdw_nread_no_pm functions
b13fac60f6f2 soundwire: bus: Remove unused reset_page_addr() callback
6b9a8b569b19 soundwire: bus: Don't zero page registers after every transaction
0583ab256805 soundwire: cadence: Drain the RX FIFO after an IO timeout
5ddae54508f1 soundwire: cadence: Remove wasted space in response_buf
056d4539db01 soundwire: cadence: Don't overflow the command FIFOs
6058024a8462 soundwire: bus_type: Avoid lockdep assert in sdw_drv_probe()

No errors or warnings in the kernel log.

Looking at the code in cadence_master.c, if I am understanding it correctly it triggers bus reset by setting CDNS_MCP_CONTROL_HW_RST. Then it waits for the Bus Reset to end by polling CDNS_MCP_CONTROL until CDNS_MCP_CONTROL_HW_RST==0.

I made a change to add a 10ms delay before starting to poll CDNS_MCP_CONTROL_HW_RST but I still see some Bus Resets are truncated.

@@ -1056,6 +1056,7 @@ void sdw_cdns_check_self_clearing_bits(struct sdw_cdns *cdns, const char *string
                dev_err(cdns->dev, "%s failed: MCP_CONFIG_UPDATE_BIT is not cleared\n", string);
 
        i = 0;
+       msleep(10);
        while (mcp_control & CDNS_MCP_CONTROL_HW_RST) {
                if (i == reset_iterations) {
                        dev_err(cdns->dev, "%s failed: MCP_CONTROL_HW_RST is not cleared\n", string);

Thank you for reporting this. I have a Soundwire analyzer setup with TGL/WHL Up Xtreme. I will try to capture the clk/data signal at the end.

SoundWire Bus Reset

A sequence of at least 4096 logic ones is generated automatically. Minimal length of hardware controlled bus reset is defined by following equation:
Reset length >= 4096+(ResetDelay*256)

@rfvirgil

@rfvirgil the reset duration is in theory programmed by software but the actual reset is handled by hardware.

As you can see from the "MCP_CONTROL_HW_RST is not cleared" logs, we have some issues on all platforms where the reset doesn't seem to complete successfully. We've been unable to root-cause it, and it's only recently that we had access to a protocol analyzer. we also added delays left and right, no luck.

What's super-suspicious is that the measured duration of the reset in 20.833 ms, exactly ONE audio sample.

soundwire: intel_bus_common: remove use of sync_arm/sync_go for hw_reset

soundwire: intel/cadence: update hardware reset sequence

@rfvirgil

@rfvirgil can you check if the PR #4225 improves the results? I followed the updated recommendation but I don't have a test rig with me.

soundwire: intel/cadence: update hardware reset sequence

@rfvirgil

closing, PR #4225 is merged and will be sent upstream. Thanks @rfvirgil for reporting and testing this.

soundwire: intel/cadence: update hardware reset sequence

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Seeing truncated Bus Reset exiting clock-stop on UpXtreme #4170

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Seeing truncated Bus Reset exiting clock-stop on UpXtreme #4170

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rfvirgil commented on Feb 2, 2023

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