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[APL][GLK] harden: power-gating and clock gating needs to be disabled during firmware download #776

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@wenqingfu

No.2 sub-task of #87.

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  1. zhuyingjiang commented on Apr 11, 2019

    @zhuyingjiang

    I think this has already been supported.

  2. mengdonglin commented on Apr 16, 2019

    @mengdonglin

    @plbossart Can this issue be closed?

  3. plbossart commented on Apr 16, 2019

    @plbossart
    Member

    I'd like a comparison with the Skylake driver (including non-upstreamed parts). The ask for all this was to doubled-check what was done in the past and make sure all known recommended sequences are supported by SOF.

  4. zhuyingjiang commented on Apr 25, 2019

    @zhuyingjiang

    @plbossart The clock/power gating for firmware download is done by PR #249 9e1dec6.
    I will submit a PR for clock/power gating for suspend/resume, and also the misc clock gating(backbone).

  5. zhuyingjiang commented on May 16, 2019

    @zhuyingjiang

    the misc clock gating part is fixed by #877.
    as suggested by Lech's mail:

    1.  PGCTL has a reversed logic. PGCTL.ADSPPG == 1 means that power gating is disabled
      

    => done by #249
    2. CGCTL.MISCBDCGE needs to be disabled during controller reset
    =>done by #877
    mark as fixed.

  6. added a commit that references this issue on May 5, 2026
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