[JCNTH]

Stack from ghstack (oldest at bottom):

• [ExecuTorch][WebGPU] Lift FastVLM dispatch limits and harden graph construction #21602
• [ExecuTorch][WebGPU] Cover Conv1d routes and dynamic manifests #21601
• -> [ExecuTorch][WebGPU] Support general groups=1 Conv1d #21600
• [ExecuTorch][WebGPU] Test byte-packed BOOL tails #21599
• [ExecuTorch][WebGPU] Support byte-packed BOOL storage #21598
• [ExecuTorch][Vulkan] Preserve persistent buffer mutations #21597
• [ExecuTorch][WebGPU] Preserve Linear and Q4 embedding params across dynamic resize #21483
• [ExecuTorch][WebGPU] Generate logical and arithmetic binary shader variants #21451
• [ExecuTorch][WebGPU] Generate extrema and unary shader variants #21450
• [ExecuTorch][WebGPU] Generate typed to_copy shader variants #21449
• [ExecuTorch][WebGPU] Make WGSL generation rollback-safe #21448
• [ExecuTorch][WebGPU] Add Qwen3 K16 attention and fp16 KV cache #21136
• [ExecuTorch][WebGPU] Add HuggingFace rotate-half RoPE #21135
• [ExecuTorch][WebGPU] Repair dynamic SDPA routing, add attestation #21134
• [ExecuTorch][WebGPU] Select emdawnwebgpu for Emscripten builds #21133
• [ExecuTorch][WebGPU] Add Llama K16 online causal attention #21132
• [ExecuTorch][WebGPU] Replace broad QKV fusion with BK64 kernel #21131
• [ExecuTorch][WebGPU] Route exact prefill shapes to the BK64 GEMM #21130
• [ExecuTorch][WebGPU] Fuse the SwiGLU elementwise chain #21129
• [ExecuTorch][WebGPU] Coordinate dynamic dispatch routes #21128
• [ExecuTorch][WebGPU] Add certified scoped output suppression #21127

Add a buffer-only groups=1 Conv1d kernel for Voxtral encoder shapes

The WebGPU backend handled only K=1 pointwise and depthwise Conv1d, leaving non-transposed groups=1 K=3 encoder convolutions unsupported.

Before

• Groups=1 K>1 graphs had no valid WebGPU route.

After

• A direct NCL buffer kernel supports groups=1 convolution with stride, padding, dilation, and optional bias.

Key changes:

• add_conv1d_node — validates fp32 operands, geometry, shapes, and shader index ranges.
• conv1d.wgsl — mirrors Vulkan output indexing in backends/vulkan/runtime/graph/ops/glsl/conv1d.glsl:78, stride/padding at :86, and the kernel FMA loop at :108.
• Dispatch and resize hooks — fold x/y workgroups and recompute live parameters safely.
• Generated sources — refresh WGSL headers, registry output, and drift digests.

The route remains limited to non-transposed groups=1 fp32 convolution; existing pointwise and depthwise routes are unchanged.

Co-authored-with: Claude Code.

Differential Revision: D114936145

[pytorch-bot]

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