An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
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Berkeley's Spatial Array Generator
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Hammer: Highly Agile Masks Made Effortlessly from RTL
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chisel tutorial exercises and answers
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A Heterogeneous GPU Platform for AI and Neural Graphics
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An open-source UCIe implementation
MLIR dialect for Atlas.
A wrapper for the SPEC CPU2006 benchmark suite.
Fletcher Lake control and programming interface API
A standalone implementation of the Tethered Serial Interface (TSI) in Python.
Gemmini extensions for Spike
exploring systematic npu codesign