phy

Opensource DDR3 Controller

An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。

Everything you need to know on how to connect the LAN8720 PHY to the ESP32.

An HDL design for sending data over Ethernet

Simple and modern C++ libraries for parsing the various Source Engine formats

Open Sigfox Stack Reference Implementation - Physical Layer for SDR

Opensource DDR4 Controller

Go package for parsing Source Engine StudioModel formats (.mdl, .vtx, .vvd, .phy)

External PHY RTL8201F with switch RTL8305NB and 2xHR871181A

Let's see how fast and accurate we could detect 5G NR slot boundary

Plugins to Phy1 - additional features to Phy

Multi-protocol physical-layer testbed orchestrator: scenario DSL, clock-alignment model, event-log builder, interference-matrix automation, and cross-protocol RF/embedded case studies (offline, stdlib-only).

ESP-NOW security overview — protocol analysis, frame capture and keyed-exchange tests on ESP32.

XTS-AES side-channel analysis - timing/EM leakage measurement and countermeasure evaluation.

Neural Signal Analysis

Python module for 5G NR sync signals and decoding.

External PHY RTL8201F with HR871181A

C++23 LoRa PHY transceiver and wideband scanner built on MIT Radio 4, paired with a Python toolchain for monitoring, decoding, and telemetry

Plugins for the manual spike sorting program phy