HBM4 System Modeling Platform - High Bandwidth Memory simulation and verification framework
132 protocol entries: 110 UVM VIPs + 22 RTL IP companions (AMBA/DDR/PCIe/CXL/USB/MIPI...) — L1-L4 SVA, smoke-verified, pyslang/iverilog/verilator gates. Apache-2.0.
Advanced SRAM Controller with ECC Support for Sky130 Process - Production-Ready Multi-Port Memory System.
Command-level DRAM/HBM timing simulator (bank state machines, tFAW/tRRD/tCCD/refresh, address mapping, FCFS/FR-FCFS) with an independent protocol checker, a DRAMsim3 cross-check and an HBM model for FHE_Accelerator_Sim — companion to the Simulation Engineering Toolkit series
Per-kernel online tuning of COSM's concurrent PIM/CPU memory controller: artifact for the IEEE CAL letter, with all scripts and data to reproduce its results.
To associate your repository with the memory-controller topic, visit your repo's landing page and select "manage topics."