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Perf: vectorised element-wise buffer loops keeping per-element atomicity (#226) - #270
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…tor accesses on arm64 (#226)
This was referenced Oct 25, 2026
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Oct 25, 2026
Fix: keep numpy buffer operations off the NEON vector path (macOS CI red since #270)
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Closes #226
On aarch64, a proven x[i] = f(...) loop over F64 buffers uses inline-asm ldr/str q helpers (precise Q operands, volatile, no C-level non-atomic access), 4 elements per step; per-element single-copy atomicity from Arm ARM DDI 0487 B2.2.1 (64-bit aligned 128-bit SIMD access = two single-copy atomic 64-bit accesses; alignment checked by tp_buf_enter). x86-64 stays scalar (Intel SDM guarantees only up to an aligned quadword). Design note records the per-target argument (the B2.2.1 wording is to be checked against the manual revision).
Scale kernel, one run, load 8.7 (not quiet): plain 0.684 ms, atomic scalar 0.853 ms (1.25x), new 0.646 ms (0.94x). Mutant (plain C store in the helper) fails the guard test. Tests: test_buffer_arrays 61, test_runtime 264, test_cgen 59, test_eval_breaker 8 passed. Merge held for the macOS runner freeze.