Introduce i.MX93 platform support

src/platform/Kconfig

@@ -125,6 +125,15 @@ config IMX8ULP
 	 Select if your target platform is imx8ulp-compatible.
 	 imx.8ulp support dsp.
 
+config IMX93_A55
+	bool "Build for NXP i.MX93 arm64 architecture (Zephyr-only)"
+	select BUILD_OUTPUT_BIN
+	select ZEPHYR_LOG
+	select HOST_PTABLE
+	select DMA_DOMAIN
+	help
+	 Select if your target platform is imx93-compatible.
+
 config RENOIR
 	bool "Build for Renoir"
 	select XT_INTERRUPT_LEVEL_5

src/platform/imx93_a55/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+add_subdirectory(lib)
+
+add_local_sources(sof platform.c)

src/platform/imx93_a55/include/platform/drivers/idc.h

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __ZEPHYR_RTOS_IDC_H__
+
+#ifndef __PLATFORM_DRIVERS_IDC_H__
+#define __PLATFORM_DRIVERS_IDC_H__
+
+#include <stdint.h>
+
+/* TODO: remove me if possible */
+
+struct idc_msg;
+
+static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
+{
+	return 0;
+}
+
+#endif /* __PLATFORM_DRIVERS_IDC_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of Zephyr's rtos/idc.h"
+
+#endif /* __ZEPHYR_RTOS_IDC_H__ */

src/platform/imx93_a55/include/platform/drivers/interrupt.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_DRIVERS_INTERRUPT_H__
+
+#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
+#define __PLATFORM_DRIVERS_INTERRUPT_H__
+
+/* TODO: remove me if possible */
+
+#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
+
+#endif /* __SOF_DRIVERS_INTERRUPT_H__ */

src/platform/imx93_a55/include/platform/lib/clk.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_LIB_CLK_H__
+
+#ifndef __PLATFORM_LIB_CLK_H__
+#define __PLATFORM_LIB_CLK_H___
+
+#define CLK_CPU(x) (x)
+#define CPU_DEFAULT_IDX 0
+#define NUM_CLOCKS 1
+#define NUM_CPU_FREQ 1
+
+struct sof;
+
+void platform_clock_init(struct sof *sof);
+
+#endif /* __PLATFORM_LIB_CLK_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/clk.h"
+
+#endif /* __SOF_LIB_CLK_H__ */

src/platform/imx93_a55/include/platform/lib/cpu.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_LIB_CPU_H__
+
+#ifndef __PLATFORM_LIB_CPU_H__
+#define __PLATFORM_LIB_CPU_H__
+
+/* note: although the core assigned to the inmate
+ * might not have the ID = 0 according to Linux,
+ * Zephyr will still index its cores starting from 0.
+ */
+#define PLATFORM_PRIMARY_CORE_ID 0
+
+#endif /* __PLATFORM_LIB_CPU_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/cpu.h"
+
+#endif /* __SOF_LIB_CPU_H__ */

src/platform/imx93_a55/include/platform/lib/dai.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_LIB_DAI_H__
+
+#ifndef __PLATFORM_LIB_DAI_H__
+#define __PLATFORM_LIB_DAI_H__
+
+/* TODO: remove me whenever possible */
+
+#endif /* __PLATFORM_LIB_DAI_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/dai.h"
+
+#endif /* __SOF_LIB_DAI_H__ */

src/platform/imx93_a55/include/platform/lib/dma.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_LIB_DMA_H__
+
+#ifndef __PLATFORM_LIB_DMA_H__
+#define __PLATFORM_LIB_DMA_H__
+
+/* i.MX93 uses dummy DMA and EDMA */
+#define PLATFORM_NUM_DMACS 2
+
+#define DMA_ID_EDMA2 0
+#define DMA_ID_HOST 1
+
+/* TODO: this is already defined with EDMA2_CHAN_MAX */
+#define PLATFORM_MAX_DMA_CHAN 64
+
+/* TODO: required by Zephyr DMA domain to work */
+#define dma_chan_irq_name(dma, chan) dma_irq_name(dma)
+#define dma_chan_irq(dma, chan) ((int *)(dma)->plat_data.drv_plat_data)[chan]
+
+#endif /* __PLATFORM_LIB_DMA_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/dma.h"
+
+#endif /* __SOF_LIB_DMA_H__ */

src/platform/imx93_a55/include/platform/lib/mailbox.h

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_LIB_MAILBOX_H__
+
+#ifndef __PLATFORM_LIB_MAILBOX_H__
+#define __PLATFORM_LIB_MAILBOX_H__
+
+/* i.MX93's mailbox is organized as follows:
+ *
+ * +---------------+----------------------+------------------------+-----------+
+ * | Region name   | Base address  | Offset |  Size   |      Permissions       |
+ * +---------------+---------------+--------+---------+------------------------+
+ * | Inbox region  |   0xce100000  |   0    | 0x1000  | ROOT: R/W, INMATE: R/W |
+ * +---------------+---------------+--------+---------+------------------------+
+ * | Outbox region |   0xce101000  | 0x1000 | 0x1000  | ROOT: R/W, INMATE: R/W |
+ * +---------------+---------------+--------+---------+------------+-----------+
+ * | Stream region |   0xce102000  | 0x2000 | 0x1000  | ROOT: R/W, INMATE: R/W |
+ * +---------------+---------------+--------+---------+------------------------+
+ *
+ *
+ * RESTRICTIONS:
+ *	* the inbox region always needs to be placed at offset 0
+ *	relative to the mailbox memory region used by the Linux host
+ *	driver. Other than that, there's no restrictions regarding the
+ *	placement of these mailbox regions.
+ *
+ * Notes:
+ *	* if there's a need to add new regions, simply append the
+ *	new regions to the above table and create memory regions
+ *	inside the Jailhouse configurations for root/inmate cells.
+ *	Also, please make sure that the Linux host driver is also
+ *	aware of these new regions.
+ *
+ *	* although these regions are placed one after the other please
+ *	note that this isn't a restriction. If there's a need to place
+ *	these regions elsewhere please not that the offset is relative
+ *	to the mailbox memory region used by the Linux host driver.
+ *
+ *	* TODO: root and inmate shouldn't have the same permissions, fix
+ *	it.
+ */
+
+/* inbox */
+#define MAILBOX_HOSTBOX_SIZE 0x1000
+#define MAILBOX_HOSTBOX_BASE 0xce100000
+#define MAILBOX_HOSTBOX_OFFSET 0
+
+/* outbox */
+#define MAILBOX_DSPBOX_SIZE 0x1000
+#define MAILBOX_DSPBOX_BASE 0xce101000
+#define MAILBOX_DSPBOX_OFFSET (MAILBOX_HOSTBOX_OFFSET + MAILBOX_HOSTBOX_SIZE)
+
+/* stream */
+#define MAILBOX_STREAM_SIZE 0x1000
+#define MAILBOX_STREAM_BASE 0xce102000
+#define MAILBOX_STREAM_OFFSET (MAILBOX_DSPBOX_OFFSET + MAILBOX_DSPBOX_SIZE)
+
+#endif /* __PLATFORM_LIB_MAILBOX_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/mailbox.h"
+
+#endif /* __SOF_LIB_MAILBOX_H__ */

src/platform/imx93_a55/include/platform/lib/memory.h

@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_LIB_MEMORY_H__
+
+#ifndef __PLATFORM_LIB_MEMORY_H__
+#define __PLATFORM_LIB_MEMORY_H__
+
+#include <rtos/cache.h>
+
+#define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE
+
+/* seems like in xtensa architecture cached data
+ * may be placed at some special addresses in the
+ * SRAM?
+ *
+ * since we're running on A55 cores, there's no such
+ * thing so all the below cache/shared data "management"
+ * functions aren't necessary.
+ */
+#define SHARED_DATA
+
+#define uncache_to_cache(address) address
+#define cache_to_uncache(address) address
+#define cache_to_uncache_init(address) address
+#define is_uncached(address) 0
+
+/* number of heaps to be used.
+ *
+ * i.MX93 is non-SMP so we're only going to use 1 heap.
+ */
+#define PLATFORM_HEAP_SYSTEM 1
+#define PLATFORM_HEAP_SYSTEM_RUNTIME 1
+#define PLATFORM_HEAP_RUNTIME 1
+#define PLATFORM_HEAP_BUFFER 1
+
+/* host and firmware use shared memory */
+#define host_to_local(addr) (addr)
+#define local_to_host(addr) (addr)
+
+/* if this gets too big then it will be
+ * necessary to increase the SRAM size from
+ * the Zephyr DTS. This should be fine as
+ * we're going to reserve 800MB for Jailhouse
+ * usage.
+ */
+#define HEAPMEM_SIZE 0x00010000
+
+/* SOF uses A side of the WAKEUPMIX MU */
+#define MU_BASE 0x42430000
+
+/* SOF uses EDMA2 (a.k.a EDMA4 in the TRM) */
+#define EDMA2_BASE 0x42010000
+#define EDMA2_CHAN_SIZE 0x8000
+
+/* WM8962 is connected to SAI3 */
+#define SAI3_BASE 0x42660000
+
+static inline void *platform_shared_get(void *ptr, int bytes)
+{
+	return ptr;
+}
+
+#endif /* __PLATFORM_LIB_MEMORY_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/memory.h"
+
+#endif /* __SOF_LIB_MEMORY_H__*/

src/platform/imx93_a55/include/platform/lib/pm_runtime.h

@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2023 NXP
+ */
+
+#ifdef __SOF_LIB_PM_RUNTIME_H__
+
+#ifndef __PLATFORM_LIB_PM_RUNTIME_H__
+#define __PLATFORM_LIB_PM_RUNTIME_H__
+
+/* TODO: is this required? Should this be implemented using Zephyr PM
+ * API?
+ */
+#include <stdint.h>
+
+struct pm_runtime_data;
+
+static inline void platform_pm_runtime_init(struct pm_runtime_data *prd)
+{
+}
+
+static inline void platform_pm_runtime_get(uint32_t context,
+					   uint32_t index,
+					   uint32_t flags)
+{
+}
+
+static inline void platform_pm_runtime_put(uint32_t context,
+					   uint32_t index,
+					   uint32_t flags)
+{
+}
+
+static inline void platform_pm_runtime_enable(uint32_t context,
+					      uint32_t index)
+{
+}
+
+static inline void platform_pm_runtime_disable(uint32_t context,
+					       uint32_t index)
+{
+}
+
+static inline bool platform_pm_runtime_is_active(uint32_t context,
+						 uint32_t index)
+{
+	return false;
+}
+
+#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h"
+
+#endif /* __SOF_LIB_PM_RUNTIME_H__ */