[keyonjie]

Mimid the SSP RX FIFO flushing logic which verified work on CNL/WHL.

We need to read out entries every time the FIFO is not empty. This
flushing may need take place several rounds, and we need to wait 1
sample time between 2 flushing rounds.

Fixes #3520

Signed-off-by: Keyon Jie yang.jie@linux.intel.com

[singalsu]

Thanks Keyon, I'll test this.

[singalsu]

I've run now the tests. It failed 2 of 3 runs, but this was the first time ever to see a single pass on BYT with sof-test check-volume-levels.sh so there is possibly improvement.

I tried to check your new traces added but even with trace verbose and my attempt to change dai_dbg() to dai_info() I still don't see traces from you patch. I wonder if the DAI drivers tracing is no more working? As sanity check I even added a custom trace print to volume component and it appeared, so there's likely something wrong in tracing.

[keyonjie]

I've run now the tests. It failed 2 of 3 runs, but this was the first time ever to see a single pass on BYT with sof-test check-volume-levels.sh so there is possibly improvement.

Thanks for testing it.

I tried to check your new traces added but even with trace verbose and my attempt to change dai_dbg() to dai_info() I still don't see traces from you patch. I wonder if the DAI drivers tracing is no more working? As sanity check I even added a custom trace print to volume component and it appeared, so there's likely something wrong in tracing.

do you mean it disappeared for volume tracing neither?

I need to get an Minnow board to test and debug it more, if tracing doesn't work for BYT thoroughly, it could take more effort to fix it.

[singalsu]

@keyonjie The traces looked normal except that none of your traces from ssp_empty_rx_fifo() appeared. My added trace elsewhere was a sanity check that I'm running the correct image with your patch included. Maybe the dai_info() and dai_dbg() are not defined for BYT SSP driver? Or this driver code wasn't running?

I would have liked to see what the before and after traced values were.

[keyonjie]

@keyonjie The traces looked normal except that none of your traces from ssp_empty_rx_fifo() appeared. My added trace elsewhere was a sanity check that I'm running the correct image with your patch included. Maybe the dai_info() and dai_dbg() are not defined for BYT SSP driver? Or this driver code wasn't running?

The dai tracing issue is addressed, UUID and TR_CTX is missed in baytail/ssp.c, it will be fixed after added those.

I would have liked to see what the before and after traced values were.

But unfortunately, after several hours debugging, it looks to me that the external wired mode looks quite similar to internal LBM for BYT SSP, the capture can't be stopped separately so the RX FIFO watermark(RFL) keep increasing even we have cleared the RSRE (while SSE is set), so, to me, this issue looks is not easy to be fixed.

Let me change this PR to draft one, I may not pay extra effort to work on this anymore.

[singalsu]

@keyonjie Thanks for the effort! It's unfortunate that the SSP registers bits specification is not friendly for FW/SW.

Nice that you were able to fix the trace.

[lgirdwood]

Any update ? you are all green.

[keyonjie]

@lgirdwood @singalsu let me close this as it doesn't fix the issue.