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mn: clear mclk and bclk source clks in MDIVCTRL #3083

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Merged
lgirdwood merged 1 commit into from
Jun 30, 2020
Merged

mn: clear mclk and bclk source clks in MDIVCTRL #3083

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15 changes: 13 additions & 2 deletions src/drivers/intel/ssp/mn.c
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Original file line number Diff line number Diff line change
Expand Up @@ -140,6 +140,9 @@ static inline int setup_initial_mclk_source(uint32_t mclk_id,
/* enable MCLK divider */
mdivc |= MN_MDIVCTRL_M_DIV_ENABLE;

/* clear source mclk clock - bits 17-16 */
mdivc &= ~MCDSS(MN_SOURCE_CLKS_MASK);

/* select source clock */
mdivc |= MCDSS(ssp_freq_sources[clk_index]);

Expand Down Expand Up @@ -375,6 +378,7 @@ static inline int setup_initial_bclk_mn_source(uint32_t bclk, uint32_t *scr_div,
uint32_t *m, uint32_t *n)
{
struct mn *mn = mn_get();
uint32_t mdivc;
int clk_index = find_bclk_source(bclk, scr_div, m, n);

if (clk_index < 0) {
Expand All @@ -384,8 +388,15 @@ static inline int setup_initial_bclk_mn_source(uint32_t bclk, uint32_t *scr_div,

mn->bclk_source_mn_clock = clk_index;

mn_reg_write(MN_MDIVCTRL, 0, (mn_reg_read(MN_MDIVCTRL, 0) |
MNDSS(ssp_freq_sources[clk_index])));
mdivc = mn_reg_read(MN_MDIVCTRL, 0);

/* clear source bclk clock - 21-20 bits */
mdivc &= ~MNDSS(MN_SOURCE_CLKS_MASK);

/* select source clock */
mdivc |= MNDSS(ssp_freq_sources[clk_index]);

mn_reg_write(MN_MDIVCTRL, 0, mdivc);

platform_shared_commit(mn, sizeof(*mn));

Expand Down
3 changes: 3 additions & 0 deletions src/platform/intel/cavs/include/cavs/drivers/mn.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,9 @@
/** \brief Bits for setting M/N source clock. */
#define MNDSS(x) SET_BITS(21, 20, x)

/** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
#define MN_SOURCE_CLKS_MASK 0x3

#endif /* __CAVS_DRIVERS_MN_H__ */

#else
Expand Down