Repository navigation
topology: cavs: switch all pipelines to timer scheduling - #1946
Conversation
|
|
To limit the number of interrupt levels processed in the system. Timer + IPC + IDC are already on level 2, DMAs are on level 5. DMIC and SSP will be the only one left on level 5, but they are raised only when hardware detects an over/underrun, so almost never. Will update the commit description. |
Thanks 4 info |
83228b6 to
871c84e
Compare
Switches all pipelines for cAVS platforms to timer scheduling. This way we limit the number of interrupt levels processed in the system. Timer, IPC and IDC are already on level 2 and DMAs are on level 5. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
871c84e to
4e0113d
Compare
Switches all pipelines for cAVS platforms to timer scheduling.
Signed-off-by: Tomasz Lauda tomasz.lauda@linux.intel.com