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topology: Update CML topologies #1774
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lgirdwood
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sathyap-chrome:remotes/sathya/master
Sep 27, 2019
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,68 @@ | ||
| # | ||
| # Topology for Cometlake with rt1011 spk on SSP1 | ||
| # | ||
|
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| # Include SOF CML RT5682 Topology | ||
| # This includes topology for RT5682, DMIC and 3 HDMI Pass through pipeline | ||
| include(`sof-cml-rt5682-kwd.m4') | ||
| include(`abi.h') | ||
| DEBUG_START | ||
| # | ||
| # Define the Speaker pipeline | ||
| # | ||
| # PCM5 ----> volume (pipe 7) ----> SSP1 (speaker - rt1011, BE link 5) | ||
| # | ||
|
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| dnl PIPELINE_PCM_ADD(pipeline, | ||
| dnl pipe id, pcm, max channels, format, | ||
| dnl frames, deadline, priority, core) | ||
|
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| # Low Latency playback pipeline 7 on PCM 5 using max 2 channels of s32le. | ||
| # Schedule 48 frames per 1000us deadline on core 0 with priority 0 | ||
| PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, | ||
| 7, 5, 2, s32le, | ||
| 1000, 0, 0, | ||
| 48000, 48000, 48000) | ||
|
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| # | ||
| # Speaker DAIs configuration | ||
| # | ||
|
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| dnl DAI_ADD(pipeline, | ||
| dnl pipe id, dai type, dai_index, dai_be, | ||
| dnl buffer, periods, format, | ||
| dnl frames, deadline, priority, core) | ||
|
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||
| # playback DAI is SSP1 using 2 periods | ||
| # Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 | ||
| DAI_ADD(sof/pipe-dai-playback.m4, | ||
| 7, SSP, 1, SSP1-Codec, | ||
| PIPELINE_SOURCE_7, 2, s24le, | ||
| 48, 1000, 0, 0) | ||
|
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| # PCM Low Latency, id 0 | ||
| dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) | ||
| PCM_PLAYBACK_ADD(Speakers, 5, PIPELINE_PCM_7) | ||
|
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| # | ||
| # BE configurations for Speakers - overrides config in ACPI if present | ||
| # | ||
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| #SSP 1 (ID: 6) | ||
| #Use BCLK delay in SSP_CONFIG_DATA only on supporting version | ||
|
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| ifelse(SOF_ABI_VERSION_3_9_OR_GRT, `1', | ||
| `DAI_CONFIG(SSP, 1, 6, SSP1-Codec, | ||
| SSP_CONFIG(DSP_A, SSP_CLOCK(mclk, 24000000, codec_mclk_in), | ||
| SSP_CLOCK(bclk, 4800000, codec_slave), | ||
| SSP_CLOCK(fsync, 48000, codec_slave), | ||
| SSP_TDM(4, 25, 3, 15), | ||
| SSP_CONFIG_DATA(SSP, 1, 24, 0, 0, 10)))', | ||
| `DAI_CONFIG(SSP, 1, 6, SSP1-Codec, | ||
| SSP_CONFIG(DSP_A, SSP_CLOCK(mclk, 24000000, codec_mclk_in), | ||
| SSP_CLOCK(bclk, 4800000, codec_slave), | ||
| SSP_CLOCK(fsync, 48000, codec_slave), | ||
| SSP_TDM(4, 25, 3, 15), | ||
| SSP_CONFIG_DATA(SSP, 1, 24)))') | ||
|
|
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| DEBUG_END |
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how was this ever merged? we played 48kHz at the wrong frequency?
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Unfortunately yes. maxim has a depenancy that BCLK should be exactly = FSYNC * CH * Bit till we had m/n divider BCLK should only be a divisior of MCLK and hence this was only working configuration available which maxim also suggested to be ok to use.
With m/n divider now available, we can satisfy the maxim requirement by giving 2.304 Mhz BCLK.