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cavs: ipc: added ipc received and processed counters #1441

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Merged
lgirdwood merged 1 commit into from
May 27, 2019
Merged

cavs: ipc: added ipc received and processed counters #1441

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8 changes: 8 additions & 0 deletions Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -140,4 +140,12 @@ config BUILD_VM_ROM
help
Select if you want to build VM ROM

config DEBUG_IPC_COUNTERS
bool "IPC counters"
depends on CAVS
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depends on DEBUG
default n
help
Select for enabling tracing IPC counter in SRAM_REG mailbox

endmenu
26 changes: 26 additions & 0 deletions src/drivers/intel/cavs/ipc.c
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Expand Up @@ -56,6 +56,24 @@

extern struct ipc *_ipc;

#if CONFIG_DEBUG_IPC_COUNTERS
static inline void increment_ipc_received_counter(void)
{
static uint32_t ipc_received_counter;

mailbox_sw_reg_write(SRAM_REG_FW_IPC_RECEIVED_COUNT,
ipc_received_counter++);
}

static inline void increment_ipc_processed_counter(void)
{
static uint32_t ipc_processed_counter;

mailbox_sw_reg_write(SRAM_REG_FW_IPC_PROCESSED_COUNT,
ipc_processed_counter++);
}
#endif

/* test code to check working IRQ */
static void ipc_irq_handler(void *arg)
{
Expand Down Expand Up @@ -93,6 +111,10 @@ static void ipc_irq_handler(void *arg)
/* mask Busy interrupt */
ipc_write(IPC_DIPCCTL, dipcctl & ~IPC_DIPCCTL_IPCTBIE);

#if CONFIG_DEBUG_IPC_COUNTERS
increment_ipc_received_counter();
#endif

@keyonjie keyonjie May 17, 2019

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How about those "dropping msg" happened in line 117? At the case handled_counter will be never equal to recceived_counter?

@bkokoszx bkokoszx May 17, 2019 •
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@keyonjie
If I understand correctly in our current IPC flow, we do not have any IPC's queuing. Driver can send new IPC only when firmware accomplishes previous ipc task and triggers interrupt to host.
It happens in 177 line:

ipc->host_pending = 0;
/* write 1 to clear busy, and trigger interrupt to host*/
#if CAVS_VERSION == CAVS_VERSION_1_5
	ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) | IPC_DIPCT_BUSY);

So in current flow we will never have situation that the variable _ipc->host_pending will be set to true in line 117.

/* TODO: place message in Q and process later */
/* It's not Q ATM, may overwrite */
if (_ipc->host_pending) {
Expand Down Expand Up @@ -174,6 +196,10 @@ void ipc_platform_do_cmd(struct ipc *ipc)
ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) | IPC_DIPCTDA_BUSY);
#endif

#if CONFIG_DEBUG_IPC_COUNTERS
increment_ipc_processed_counter();
#endif

/* unmask Busy interrupt */
ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE);

Expand Down
10 changes: 6 additions & 4 deletions src/platform/apollolake/include/platform/memory.h
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Expand Up @@ -258,10 +258,12 @@
#define SRAM_SW_REG_SIZE 0x1000

/* SRAM window 0 FW "registers" */
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_END 0xc
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_END 0x14

#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
#define SRAM_OUTBOX_SIZE 0x1000
Expand Down
10 changes: 6 additions & 4 deletions src/platform/cannonlake/include/platform/memory.h
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Expand Up @@ -203,10 +203,12 @@
#define SRAM_SW_REG_SIZE 0x1000

/* SRAM window 0 FW "registers" */
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_END 0xc
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_END 0x14

#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
#define SRAM_OUTBOX_SIZE 0x1000
Expand Down
10 changes: 6 additions & 4 deletions src/platform/icelake/include/platform/memory.h
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Expand Up @@ -206,10 +206,12 @@
#define SRAM_SW_REG_SIZE 0x1000

/* SRAM window 0 FW "registers" */
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_END 0xc
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_END 0x14

#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
#define SRAM_OUTBOX_SIZE 0x1000
Expand Down