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[BUG] glitch in 17_06_TestMultiCoreCompSrcPlb8000Hz16b16b1ch test #4050

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[BUG] glitch in 17_06_TestMultiCoreCompSrcPlb8000Hz16b16b1ch test#4050
Labels
ICLApplies to IceLake platformTGLApplies to Tiger LakeWHLApplies to WhiskeyLake platformbugSomething isn't working as expectedcomponent-level multicoreIssues observed when scenario when pipeline components are split across different coresdiagnostic driverSlim driver / diagnostic driver issueduplicateThis issue or pull request already existsmulticoreIssues observed when not only core#0 is used.

Description

@kkarask
kkarask
opened on Apr 19, 2021

Describe the bug
In test 17_06_TestMultiCoreCompSrcPlb8000Hz16b16b1ch glitch was found.

Topology

                    pipe_plb core 0, src core 1
           +--------------------------------+
    +----+ | +---+  +---+  +---+  +-------+ |
    |Host|-->|Buf|->|Src|->|Buf|->|SSP Dai|---+
    +----+ | +---+  +---+  +---+  +-------+ | |
           +--------------------------------+ |
                    pipe_cap core 0           |
           +------------------+               |
    +----+ | +---+  +-------+ |               |
    |Host|<--|Buf|<-|SSP Dai|<----------------+
    +----+ | +---+  +-------+ |
           +------------------+

To Reproduce
Run test with Diagnostic driver 17_06_TestMultiCoreCompSrcPlb8000Hz16b16b1ch.

Reproduction Rate
Sporadic.

Environment

  1. Branch name and commit hash of the 2 repositories: sof (firmware/topology) and linux (kernel driver).

  2. Name of the platform(s) on which the bug is observed.

    • Platform: ICL RVP

  3. Test environment:
    BRANCH: master HASH: b7ed915d911acda055bbb822800b76557e9fe7de

Screenshots or console output
image

2021_04_18_00_45_36.zip

Activity

  1. kkarask
    added
    bugSomething isn't working as expected
    on Apr 19, 2021
  2. zrombel
    added
    ICLApplies to IceLake platform
    on Apr 19, 2021
  3. zrombel
    assigned
    slawblauciak
    on Apr 19, 2021
  4. mengdonglin
    added
    multicoreIssues observed when not only core#0 is used.
    on May 7, 2021
  5. kkarask
    added
    WHLApplies to WhiskeyLake platform
    on May 11, 2021

  6. kkarask commented on May 11, 2021

    @kkarask
    kkarask
    on May 11, 2021
    Author

    I run stress tests and found glitch in the whole wav file in test: 17_03_TestMultiCoreMultiKernelHda48000hz16b16b4ch on WHL platform.
    Reproduction rate: 1/75.

    Topology:

     pipe_plb core 0
                    +--------------------+
    +----------+    | +------+   +-----+ |   +-----+
    | Host plb |----->|Buffer|-->| Dai |---->|codec|
    +----------+    | +------+   +-----+ |   +-----+
                    +--------------------+    |  |
                                              |  |
                    pipe_cap core 1           |  |
                    +--------------------+    |  |
    +----------+    | +------+   +-----+ |   +-----+
    | Host cap |<-----|Buffer|<--| Dai |---->|codec|
    +----------+    | +------+   +-----+ |   +-----+
                    +--------------------+

    Branch: main, hash: 37d97d4

    17_03_TestMultiCoreMultiKernelHda48000hz16b16b4ch.zip

  7. lgirdwood
    added
    duplicateThis issue or pull request already exists
    on May 13, 2021

  8. lgirdwood commented on May 13, 2021

    @lgirdwood
    lgirdwood
    on May 13, 2021
    Member

    Duplicate of simpler #4076

  9. mengdonglin
    added
    component-level multicoreIssues observed when scenario when pipeline components are split across different cores
    on Jun 7, 2021
  10. wszypelt
    added
    diagnostic driverSlim driver / diagnostic driver issue
    on Jun 11, 2021
  11. kkarask
    added
    TGLApplies to Tiger Lake
    on Jun 22, 2021

  12. kkarask commented on Jun 22, 2021

    @kkarask
    kkarask
    on Jun 22, 2021
    Author

    Problem with multi core was found also in test 17_07_TestMultiCoreSrcCap48000Hz32b32b8ch in capture pipeline where src component is on core 1:

    pipeline playback core 0
           +------------------+
    +----+ | +---+  +-------+ |
    |Host|-->|Buf|->|SSP Dai|----------------->+
    +----+ | +---+  +-------+ |                |
           +------------------+                |
        pipeline capture core 0, src core 1    |
           +--------------------------------+  |
    +----+ | +---+  +---+  +---+  +-------+ |  |
    |Host|<--|Buf|<-|Src|<-|Buf|<-|SSP Dai|<---+
    +----+ | +---+  +---+  +---+  +-------+ |
           +--------------------------------+

    Reproduction rate: 3/75

    Branch: main, Hash: d5d2b41

    Platforms: TGL RVP, ICL RVP

    image

    ICL_17_07_TestMultiCoreSrcCap48000Hz32b32b8ch.zip

  13. slawblauciak
    removed their assignment
    on Aug 2, 2021

  14. wszypelt commented on Jan 2, 2023

    @wszypelt
    wszypelt
    on Jan 2, 2023

    TGL issue does not occur
    Tested FW hash: 4943aaa

  15. wszypelt
    closed this as completedon Jan 2, 2023
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    ICLApplies to IceLake platformTGLApplies to Tiger LakeWHLApplies to WhiskeyLake platformbugSomething isn't working as expectedcomponent-level multicoreIssues observed when scenario when pipeline components are split across different coresdiagnostic driverSlim driver / diagnostic driver issueduplicateThis issue or pull request already existsmulticoreIssues observed when not only core#0 is used.

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