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[BUG IMX] Input/output error when do simultaneous playback/capture test #3690
Our DMA controller has 32 channels but only two are used for this scenario so having dma_domain->data->data[i][j].task = NULL is legit.
I wonder why this is not happening on Intel platforms. Are always all the channels started?
No - only 1 channel is used per stream on Intel HW. However, on some platforms the DMA IRQ is shared by all the channels.
I would also prefer 2. @dbaluta btw, any ETA for CI for IMX ? I guess you have CI for Zephyr, so you could get CI for free when your Zephyr port is done ?
@lgirdwood you mean that when doing a dma irq clear on a channel, this might change the status on other channels too?
One more thing, regarding #3339 - when reading the commit message I see that it 's possible to have multiple tasks on the same channel, but in the code (ll_schedule.c and dma_multi_chan_domain.c) we only look for one task per channel. Am I missing something here?
Our DMA controller has 32 channels but only two are used for this scenario so having dma_domain->data->data[i][j].task = NULL is legit.
I wonder why this is not happening on Intel platforms. Are always all the channels started?
No - only 1 channel is used per stream on Intel HW. However, on some platforms the DMA IRQ is shared by all the channels.
I would also prefer 2. @dbaluta btw, any ETA for CI for IMX ? I guess you have CI for Zephyr, so you could get CI for free when your Zephyr port is done ?
Best we could do is to setup an internal CI. And now we switched to 5.10 and stable-v1.6. I will talk with Zephyr guys to see what they have in terms of CI.
Biggest stopper is that there are some architecture patches on imxes which are not yet upstream so using topic/sof-dev is out of the question for now.
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dbaluta commentedon Dec 15, 2020
@lyakh @iuliana-prodan
Regression introduced by #3339
This happens because we reach https://github.com/thesofproject/sof/blob/master/src/schedule/dma_multi_chan_domain.c#L296
with
dma_domain->data[i][j].task = NULLOur DMA controller has 32 channels but only two are used for this scenario so having
dma_domain->data->data[i][j].task = NULLis legit.I wonder why this is not happening on Intel platforms. Are always all the channels started?
We have two possible solutions for this problem:
I would go for option 2) but need some guidance on this.
lgirdwood commentedon Dec 17, 2020
No - only 1 channel is used per stream on Intel HW. However, on some platforms the DMA IRQ is shared by all the channels.
I would also prefer 2.
@dbaluta btw, any ETA for CI for IMX ? I guess you have CI for Zephyr, so you could get CI for free when your Zephyr port is done ?
iuliana-prodan commentedon Dec 17, 2020
@lgirdwood you mean that when doing a dma irq clear on a channel, this might change the status on other channels too?
One more thing, regarding #3339 - when reading the commit message I see that it 's possible to have multiple tasks on the same channel, but in the code (ll_schedule.c and dma_multi_chan_domain.c) we only look for one task per channel. Am I missing something here?
dbaluta commentedon Dec 17, 2020
Best we could do is to setup an internal CI. And now we switched to 5.10 and stable-v1.6. I will talk with Zephyr guys to see what they have in terms of CI.
Biggest stopper is that there are some architecture patches on imxes which are not yet upstream so using topic/sof-dev is out of the question for now.
schedule: dma_multi_chan: fix null pointer when scanning for tasks
schedule: dma_multi_chan: fix null pointer when scanning for tasks
schedule: dma_multi_chan: fix null pointer when scanning for tasks