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plbossart
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I don't understand why you enable 2 cores by default, and I have questions on the changes that have nothing to do with the rom timeout.
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@plbossart This is a bug, using goto will dump and call powerdown two times. so if fail, just return.
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@zhuyingjiang sorry, I don't see what would cause this loop to be executed twice. the flow is quite unclear to me here.
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this is really not related to the timeout, you need to provide patches that match the commit message
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Why would you use 2 cores by default? This makes no sense. It's not because you can that you should, it's horrible in terms of power consumption.
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iirc, this is copied exactly from SKL driver.
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@lgirdwood @zhuyingjiang I dont think the SKL driver does this. But even if it does, we have the means to bring up the cores when there are pipelines scheduled to run on them. I dont think it is necessary to power them all up at boot.
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OK, let's keep only one core enabled at first, so just remove the second commit is OK.
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@plbossart Updated |
plbossart
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the explanations on patch2 aren't clear to me. You know I am paranoid about error flows so I'd like to understand a bit more what problem this patch2 solves.
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@zhuyingjiang sorry, I don't see what would cause this loop to be executed twice. the flow is quite unclear to me here.
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@plbossart It is not loop twice, when cl_dsp_init_skl can't enable the core, it will return a ret which is less than 0, and will execute the following flow inside cl_dsp_init_skl to dump the registers and reset/power down the core:
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@zhuyingjiang the sequence in boot_firmware() in loader.c has recently been updated to do a proper cleanup in case of failures. Could you please take a look and align the skl loader along similar lines? |
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Agree with @ranj063 the error flow doesn't seem quite right |
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@plbossart @ranj063 Thanks for the comments, I am working on the S3 issue and will change this PR some later. |
@ranj063 |
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@zhuyingjiang the skl loader needs a bit of rework. here're my comments:
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@ranj063 seems what you mention is not related to the "ROM init timeout", Should that go with another refine PR? I heard that it will lost track if the title message and the code are not related. |
Yes,please. |
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OK, I removed the "skl fix a bug of error handle" commit and keep the commit for "skl make ROM init timeout skl specific" and "skl fix some comments error". @plbossart @ranj063 Could you approve and merge the kept ROM init part? I will create a issue and a follow PR to refine the skl loader code. |
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@zhuyingjiang i just looked back into my PR and i've not touched the HDA_DSP_INIT_TIMEOUT but only removed the HDA_ROM_INIT_TIMEOUT. Although it looks like we should be using the rom init timeout here, I wonder why we were using HDA_DSP_INIT_TIMEOUT before.
How did you test this? I am confused about whether this is correct or not.
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besides the register poll method has been changed recently. Can you please fix the conflicts?
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besides the register poll method has been changed recently. Can you please fix the conflicts?
Done.
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@ranj063 As I have mentioned in #704
Yes, SKL still need this timeout. As I test, the HDA_ROM_INIT_TIMEOUT which is 70ms is some short, So I use the already defined HDA_DSP_INIT_TIMEOUT 500ms, If this can be platform specific, 150 ms can work for SKL.
@zhuyingjiang sorry I missed the previous comment. Thanks
make ROM init timeout platform specific, change from define to platform structure assigned. Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com>
fix two comments, Apollolake should be Skylake Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com>
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@plbossart Could you approve and merge this? I will create a issue and follow a PR to do the refine of skl code loader. |
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@zhuyingjiang I will merge this one but this is the last one. I don't want anything related to SKL unless we have a real plan to support this platform.
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@plbossart OK, thanks! |
As part of #704
make the ROM init timeout SKL platform specific, setting to 150 ms.
change the core mask, so the two cores can be enabled.
unlike DSP core of APL, CNL which must power up, reset and unstall core 0 first, the SKL DSP cores can be enabled at the same time.