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soundwire: intel_auxdevice: start the bus at default frequency - #5064
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ok, https://sof-ci.01.org/linuxpr/PR5064/build3672/devicetest/index.html is good except for known alsa-bat issues. Let's try to simplify further. |
When platform firmware exposes multiple supported bus frequencies, the existing SoundWire support selects the maximum frequency. This is not aligned with the SoundWire 1.2 directions: the MIPI recommendation is to start at a 'safe' speed, compatible with the default frame rate and shape, and only increase the clock when vendor and codec PHY parameters are updated. However, clock changes are not supported for now by the SoundWire core, so in practice this patch has the effect of discarding frequencies different to the implicit default. Dynamic clock changes will be required at some point, and this limitation will be removed after the core is updated, specifically to perform synchronous clock scale changes on manager and peripheral sides with a bank switch. On Intel LunarLake platforms with a 'standard' DSDT, this forces the use of 4.8MHz. On older platforms this patch has no effect. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
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results look good for SDW AIOC @bardliao I'd like to merge this since it's a really bad problem impacting all PRs. Merging on a Friday isn't great but I think it'd help @kv2019i track the 2.10 issues. |
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I am going to make the executive decision of merging at 4pm on a Friday... Worst case we can always fix up this patch, best case we have better test reports |
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When platform firmware exposes multiple supported bus frequencies, the existing SoundWire support selects the maximum frequency. This is not aligned with the SoundWire 1.2 directions: the MIPI recommendation is to start at a 'safe' speed, compatible with the default frame rate and shape, and only increase the clock when vendor and codec PHY parameters are updated.
However, clock changes are not supported for now by the SoundWire core, so in practice this patch has the effect of discarding frequencies different to the implicit default. Dynamic clock changes will be required at some point, and this limitation will be removed after the core is updated, specifically to perform synchronous clock scale changes on manager and peripheral sides with a bank switch.
On Intel LunarLake platforms with a 'standard' DSDT, this forces the use of 4.8MHz. On older platforms this patch has no effect.