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ASoC: SOF: Intel: HDA: correct ROM status mask - #1089
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@ClarexZhou can you help try if this PR can fix #969 please? @xiulipan as discussed, may be helpful for your boot failure also. |
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kv2019i
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Thanks, looks good now!
plbossart
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the commit message can be improved.
"Without this change, we treated status like 0x6000021 (0x1 as the lowest
4 bits) as HDA_DSP_ROM_INIT (0x1 as the lowest 4 bits)"
This value 0x6000021 is not listed as a valid code in the defines, so this looks like a work-around without fixing the root cause. Or you have to explain what this code is and what using the full 8 bits will do.
While we are at it, it's very odd to have a mix of hex and decimal values as error codes. this is ugly and should be fixed.
Also you have a grammar error, it's "downloading too early", not "too earlier"
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@plbossart @keyonjie wrote:
I was trying earlier today to find a good reference for this when reviewing. Probably this is best: ROM_STATUS has values larger than 0xf, so the patch seems correct. And if this indeed helps with #969 , this is a very nice find (given the difficult of reproducing the problem). But yeah, some background on 0x6000021 would be good. I believe ROM uses similar approach as FW_STATUS to use upper 24bit to report state while processing is ongoing (documented in above link). @keyonjie can you confirm this? |
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I am also a bit confused about the commit message. I agree that 0xff is the right status mask but then the INIT_DONE status is only 0x1. So do you mean to say that 0x21 isnt the right status and should be ignored until the 0x01 is read? |
yes. |
Yes, the above link you provided is for APL, for 1.8, I believe they have extended the state that's why we are seeing 0x21 on CNL/WHL/TGL. Maybe a new page in the document for 1.8 will be helpful, @jajanusz can you help on that? |
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@keyonjie how about something like this: |
As I just replied to @kv2019i, the 0x21 is new extended in cAVS 1.8, that's why we don't see it the document for APL. Ideally we should use 24 bits according the definition of fw_status_reg, I chose 8 bits only as what ROM used until now has not exceed 8 bits yet.
I think they are defining state macros in hex and error code in decimal in ROM header file.
Thanks, change it now. |
Thanks, but this still not addressing @plbossart's comment about what 0x6000021 is, and why it is the 8 LSB bits. I am considering to drop this description about 0x6000021, and change the mask to lowest 24 bits, any comment? @ranj063 @plbossart @kv2019i |
@keyonjie yes, I think it is the right thing to do. |
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@keyonjie pointing to the APL ROM documentation will make people wonder if it applies to all platforms. Can you please clarify it in the commit message? |
What do you mean by extended the state? vs what is in docs: doesn't change the fact that it works as it is in docs, these 4 bits (noted as wait_state) are handled in the same way anyway. It depends on how you look at |
I meant new 0x21(xx_IPC_RESET_PHASE_1) added for 1.8 only.
Thanks for explaining @jajanusz , yes, that's true, previously we only used the LSB 4 bits of the state, here we are correcting it to use the whole LSB 24 bits. |
A pedantic note @jajanusz @keyonjie : bitfields in C are highly compiler and platform dependent, so in documenting binary interfaces (seen by multiple CPUs), better to simply use plain ol' bitmasks and document endianess. Here also mismatch between use of "state" and "status" is confusing. Anyways, patch looks good! |
We don't use them in FW code, these bitfields are from rom code that we don't develop ;) |
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| /* ROM status/error values */ | ||
| #define HDA_DSP_ROM_STS_MASK 0xf | ||
| #define HDA_DSP_ROM_STS_MASK 0xffffff |
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GENMASK(23, 0)?
this will be an upstream comment so might as well fix it now.
The ROM state is represented by the 24 LSB bits in the ROM status register, so the mask should be 0xffffff instead of 0xf. Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
We are using the lowest 2 digits of the ROM status register to denote
the status code, so the mask for it should be 0xff, here correct it.
Signed-off-by: Keyon Jie yang.jie@linux.intel.com