[BUG] Illegal instruction (SIGILL) on Intel Xeon E5-2680 (AVX but no AVX2) - container crash loop #48

Describe the Bug

The prizz/opencode-cloud-sandbox container enters a continuous restart loop with Illegal instruction right after the broker starts listening on the socket. This occurs on CPUs that support AVX but do not support AVX2.

To Reproduce

Steps to reproduce the behavior:

1. Run the official quick-deploy script:
   curl -fsSL https://raw.githubusercontent.com/pRizz/opencode-cloud/main/scripts/quick-deploy.sh | bash
2. Wait for the container to start and print the IOTP.
3. Observe the container crash shortly after opencode-broker starts.

Expected Behavior

The container should start successfully and remain running, allowing access to the web UI and completion of the initial passkey enrollment.

Actual Behavior

After printing the IOTP and starting the broker, the process immediately crashes with:
Illegal instruction
The container then enters a restart loop (Restarting (132)).

Environment

• OS: Debian (running as a VM under Proxmox VE)
• CPU: Intel Xeon E5-2680 @ 2.70GHz (Sandy Bridge-EP, 2012) — supports AVX, does not support AVX2
• PVE CPU type: host
• opencode-cloud version: v25.1.3 (image: prizz/opencode-cloud-sandbox:latest)
• Installation method: official quick-deploy script
• Docker version: 29.6.1
• Compose version: v5.3.1

Logs

[opencode-cloud] Starting opencode on 0.0.0.0:3000
2026-07-22T14:13:48.771484Z INFO opencode_broker: opencode-broker starting
2026-07-22T14:13:48.771862Z INFO opencode_broker: configuration loaded socket_path=/run/opencode/auth.sock pam_service=opencode rate_limit=5
2026-07-22T14:13:48.772107Z INFO opencode_broker::ipc::server: server listening path=/run/opencode/auth.sock
Illegal instruction

(The same error repeats on every restart attempt.)

Additional Context

• Official OpenCode (non-cloud version) has been successfully installed and run on this same machine previously.
• This suggests the pre-built binaries inside the current sandbox image may be compiled with a higher CPU baseline (e.g. x86-64-v3 / AVX2).
• Request: Please consider providing a baseline (older-CPU compatible) image, or document the minimum required instruction set. Happy to test any proposed fixes or rebuild instructions.