can't build: ValueError: Cannot extract CSR name from code, need to specify. #29

INFO: The saved Python interpreter does not exist or broken. Trying to find another one.
WARNING: Project requires a python version of >=3.10, The virtualenv is being created for you as it cannot be matched to the right version.
INFO: python.use_venv is on, creating a virtualenv for this project...
Virtualenv is created successfully at /home/user/Downloads/orbtrace/.venv
Synchronizing working set with resolved packages: 32 to add, 0 to update, 0 to remove

  ✔ Install iniconfig 2.0.0 successful
  ✔ Install litehyperbus 0.0.0 successful
  ✔ Install idna 3.10 successful
  ✔ Install litespi 0.0.0 successful
  ✔ Install pluggy 1.5.0 successful
  ✔ Install colorama 0.4.6 successful
  ✔ Install packaging 24.2 successful
  ✔ Install construct 2.10.70 successful
  ✔ Install certifi 2025.1.31 successful
  ✔ Install pyvcd 0.4.1 successful
  ✔ Install jinja2 3.1.5 successful
  ✔ Install pyusb 1.3.1 successful
  ✔ Install cobs 1.2.2 successful
  ✔ Install jschon 0.11.1 successful
  ✔ Install amaranth 0.5.4 successful
  ✔ Install requests 2.32.3 successful
  ✔ Install pyserial 3.5 successful
  ✔ Install libusb1 3.2.0 successful
  ✔ Install rfc3986 2.0.0 successful
  ✔ Install usb-protocol 0.9.1 successful
  ✔ Install migen 0.9.2 successful
  ✔ Install pytest 9.0.2 successful
  ✔ Install luna-usb 0.2.0 successful
  ✔ Install urllib3 2.3.0 successful
  ✔ Install litex-boards 0.0.0 successful
  ✔ Install markupsafe 3.0.2 successful
  ✔ Install pygments 2.19.2 successful
  ✔ Install charset-normalizer 3.4.1 successful
  ✔ Install litex 2023.12 successful
  ✔ Install pythondata-cpu-vexriscv 1.0.1.post407 successful
  ✔ Install pythondata-software-compiler-rt 0.0.post6206 successful
  ✔ Install pythondata-software-picolibc 1.7.9.post181 successful
  ✔ Install orbtrace 1.4.4.dev1+gca2149e.d20251226 successful

  0:00:03 🎉 All complete! 32/32

/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/export.py:100: SyntaxWarning: invalid escape sequence '\d'
  version = float(re.findall("\d+\.\d+", l)[-1])
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cva6/core.py:47: SyntaxWarning: invalid escape sequence '\$'
  res = re.search('\$\{(CVA6_REPO_DIR|LX_CVA6_CORE_DIR)\}/(.+)', l)
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cva6/core.py:53: SyntaxWarning: invalid escape sequence '\+'
  if re.match('\+incdir\+', l):
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/openc906/core.py:64: SyntaxWarning: invalid escape sequence '\$'
  res = re.search('\$\{CODE_BASE_PATH\}/(.+)', l)
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/openc906/core.py:66: SyntaxWarning: invalid escape sequence '\+'
  if re.match('\+incdir\+', l):
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e41p/core.py:67: SyntaxWarning: invalid escape sequence '\$'
  res = re.search('\$\{DESIGN_RTL_DIR\}/(.+)', l)
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e41p/core.py:69: SyntaxWarning: invalid escape sequence '\+'
  if re.match('\+incdir\+', l):
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e40p/core.py:80: SyntaxWarning: invalid escape sequence '\$'
  res = re.search('\$\{DESIGN_RTL_DIR\}/(.+)', l)
/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e40p/core.py:82: SyntaxWarning: invalid escape sequence '\+'
  if re.match('\+incdir\+', l):
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2025-12-26 23:58:06)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : LFE5U-25F-8BG256C.
INFO:SoC:System clock: 75.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
Traceback (most recent call last):
  File "/home/user/Downloads/orbtrace/.venv/bin/orbtrace_builder", line 8, in <module>
    sys.exit(main())
             ~~~~^^
  File "/home/user/Downloads/orbtrace/orbtrace_builder.py", line 78, in main
    soc = OrbSoC(
        platform = platform,
    ...<11 lines>...
        **soc_core_argdict(args)
    )
  File "/home/user/Downloads/orbtrace/orbtrace/soc.py", line 51, in __init__
    SoCCore.__init__(self, platform, sys_clk_freq,
    ~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        ident          = 'LiteX SoC for Orbtrace',
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        **kwargs)
        ^^^^^^^^^
  File "/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/soc_core.py", line 208, in __init__
    self.add_controller("ctrl")
    ~~~~~~~~~~~~~~~~~~~^^^^^^^^
  File "/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/soc.py", line 992, in add_controller
    self.add_module(name=name, module=SoCController(**kwargs))
                                      ~~~~~~~~~~~~~^^^^^^^^^^
  File "/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/soc.py", line 831, in __init__
    self._reset = CSRStorage(fields=[
                  ~~~~~~~~~~^^^^^^^^^
        CSRField("soc_rst", size=1, offset=0, pulse=True, description="""Write `1` to this register to reset the full SoC (Pulse Reset)"""),
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        CSRField("cpu_rst", size=1, offset=1,             description="""Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)"""),
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    ])
    ^^
  File "/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/interconnect/csr.py", line 388, in __init__
    _CompoundCSR.__init__(self, size, name, n)
    ~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^
  File "/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/interconnect/csr.py", line 136, in __init__
    _CSRBase.__init__(self, size, name, n)
    ~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^
  File "/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/interconnect/csr.py", line 53, in __init__
    raise ValueError("Cannot extract CSR name from code, need to specify.")
ValueError: Cannot extract CSR name from code, need to specify.