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perf(gemm): native float32 GEMM on riscv64 - #80

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@tannevaled tannevaled commented Oct 31, 2026 •

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Native float32 GEMM on riscv64: gemmMicro6x16RVV (RVV, E32/LMUL=4, vl=16 on any VLEN ≥ 128), gated on useRVV.

  • Correctness: the kernel and root suites pass on a real Spacemit X60 (cfarm95).
  • Sabotage check: shifting the A rows made only the qemu riscv64 lane fail, and the sabotage commit has been removed.

Still a draft: not measured. The X60 host was 98.9% busy (load 19 on 8 cores) and abbench refused to run. This merges once an A/B on a quiet host shows the gain; the docs come with that measurement.

🤖 Generated with Claude Code

gemmMicro6x16RVV is the float64 6x8 RVV kernel in float32: with E32,
a group of four registers (LMUL=4) holds at least sixteen floats on any
VLEN >= 128, so vl = 16 everywhere and the same six accumulator groups,
B group and C group fit. Each A value is fused in with vfmacc.vf. Gated
on useRVV; without V, float32 products widen to the float64 GEMM.

Correct on a real Spacemit X60 (cfarm95), kernel and root suites. Not
yet measured: the host was 98.9% busy and abbench refused to run.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@tannevaled

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Superseded by #108: the same kernel, rebased onto today's main and measured on the X60 (−51% to −69% against the float64 path; still 1.26–1.69× slower than OpenBLAS, filed as #107). The rebase is on a new branch because a force-push of this one was refused; this branch is left as it was.

🤖 Generated with Claude Code

@tannevaled tannevaled closed this Nov 9, 2026
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