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floats v0.10.0: drop the max/min zero fallback and the moved sum/elementwise assembly - #100

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perf/floats-v0.10.0
Nov 7, 2026
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perf/floats-v0.10.0

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Bumps go-simd/floats to v0.10.0 and uses it:

  • amd64/arm64 maxSIMD/minSIMD return floats.Max/Min (signed zeros fixed in floats#32), so the serial fallback for a zero result is removed.
  • ppc64le, loong64, riscv64, s390x: float64 sqrt and add/sub/mul/div come from floats (floats#30); the dead float64 sum assembly and the moved elementwise kernels are deleted from the asmgen generators and regenerated sum_<arch>.s (amd64/arm64 output identical).
  • amd64 without AVX2+FMA gets floats SSE2 kernels (floats#31).

Verified: go test ./... on arm64, go vet for the five other targets, native IBM z17 go test ./internal/kernels (cross-compiled, scp). The qemu lanes of CI cover ppc64le, loong64, riscv64. Max/Min, dot and GEMM kernels of the four architectures stay in ndarray.

🤖 Generated with Claude Code

… four-arch elementwise asm

- go-simd/floats v0.9.0 -> v0.10.0.
- maxSIMD/minSIMD (amd64, arm64) return floats.Max/Min directly: the signed-zero
  contract is floats' since floats#32, so the serial recomputation of a zero
  result is gone.
- ppc64le, loong64, riscv64, s390x: sqrtSIMD and addBin/subBin/mulBin/divBin call
  floats.Sqrt/Add/Sub/Mul/Div (floats#30: the kernels moved there with the same
  instruction sequences and gate themselves on the CPU feature). The float64
  sumVSX/sumLASX/sumRVV/sumVX (dead since v0.37.0) and the float64
  sqrt/add/sub/mul/div kernels are removed from the asmgen generators and from
  sum_<arch>.s (regenerated; amd64 and arm64 output unchanged).
- amd64 without AVX2+FMA runs floats' SSE2 kernels (floats#31).

Native IBM z17 (ssh linuxone): go test ./internal/kernels passes. Max/Min and
dot/gemm kernels of the four architectures stay here.

Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
@tannevaled
tannevaled merged commit c6f3636 into main Nov 7, 2026
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tannevaled deleted the perf/floats-v0.10.0 branch November 7, 2026 23:30
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