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1. pcie-gen3-controller-uvm pcie-gen3-controller-uvm Public

   Synthesizable PCIe Gen 3 Controller Subsystem (TL/DLL) & UVM verification suite using pyuvm, cocotb, and Verilator.

   SystemVerilog

2. non-blocking-mesi-cache non-blocking-mesi-cache Public

   4-way set-associative non-blocking cache with 8-entry MSHR, MESI hardware snooping, and AXI4 burst master in Verilog/C++/Verilator.

   SystemVerilog

3. async-fifo-sky130-timing-closure async-fifo-sky130-timing-closure Public

   Parameterized dual-clock asynchronous FIFO with Gray-code CDC synchronizers, synthesized on SkyWater 130nm via Yosys and timed with OpenSTA (400 MHz WCLK / 200 MHz RCLK).

   Verilog