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low-latency-1g-ethernet
low-latency-1g-ethernet PublicLow-latency 1G Ethernet RX in SystemVerilog: GMII to UDP payload, 0 added cycles
Python 2
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protocol-emulator-asic
protocol-emulator-asic PublicA programmable pin-bit-banging core that speaks UART, SPI, and I²C from firmware. Jane Street 2027 ASIC competition entry, targeting Tiny Tapeout on IHP CMOS5L.
C++ 1
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Orderbook-cpp
Orderbook-cpp PublicC++ golden model of a NASDAQ ITCH 5.0 limit order book for future RTL/FPGA implementation.
C++ 3
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options_backtest
options_backtest PublicC++20 backtesting engine for NSE options — covered calls, losing-month diagnostics, and a static-export web UI
C++
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