You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
{{ message }}
Repository navigation
L4 dataflow: formal_in ports have no outgoing ddg; statement↔actual-port links absent (partial twin of the canpy port-layer gap) #80
Twin of the codeanalyzer-python L4 port-layer audit (filed today; found during python-sdk#270 verb validation). On the cants L4 sample in python-sdk (tests/resources/cpg/ts-a4.json):
formal_in ports: 2, 0 with outgoing ddg — parameter flow entering via param_in dead-ends at the port (the @entry → stmt var edges duplicate the role).
No stmt → actual_in or actual_out → stmt edges observed — argument-binding and return-value-binding at call sites are missing, so cross-callable flows_to witnesses are port-to-port segments only.
Caveat: the committed sample is small (one call site); please verify the absence classes on a larger -a 4 corpus before scoping — the canpy audit used a 758-callable corpus and the pattern there was categorical (zero port-touching ddg edges of any class).
Missing edge checklist (same as canpy, minus the return side already done):
def stmt → actual_in:k
actual_out → use stmt
formal_in:k → first-use stmts
Also worth checking whether TS call vertices sit on the CFG spine (canpy's are 100% cfg-orphaned).
Verified on a larger corpus as asked, before scoping: dataflow-app at -a 4, 33 callables, 24 formal_in / 20 actual_in / 21 actual_out vertices — zero port-touching ddg edges of any class except statement → formal_out (31). Categorical, same shape as canpy's audit. Fixed together with #81 in the PR above; the side question here (are TS call vertices on the CFG spine?) is answered by the same measurement — statement → call, entry → call and call → statement edges exist, so unlike python's they are not cfg-orphaned.
Activity
rahlk commentedon Sep 6, 2026
Verified on a larger corpus as asked, before scoping:
dataflow-appat-a 4, 33 callables, 24formal_in/ 20actual_in/ 21actual_outvertices — zero port-touching ddg edges of any class exceptstatement → formal_out(31). Categorical, same shape as canpy's audit. Fixed together with #81 in the PR above; the side question here (are TScallvertices on the CFG spine?) is answered by the same measurement —statement → call,entry → callandcall → statementedges exist, so unlike python's they are not cfg-orphaned.fix(dataflow): connect the L4 port lattice to the statement ddg
fix(dataflow): connect the L4 port lattice to the statement ddg (#169)