Synthesizable 100 MHz+ Text, Vision & Audio Conformer Embedding Accelerators · Intel Arria 10 GX PCIe Gen3x8 HIL · IEEE/ACM Dual-Track Reports
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Website · Vulcan Showcase · Anvil-Q (LLM) · Anvil-E (Embedding) · Billet-T (FFT/DSP) · Billet-F (FIR/IIR) · Rivet-A (AES-GCM) · Rivet-H (SHA/HMAC) · Swage-S (ISP) · Bellows-L (LZ4) · Crucible-G (3D) · Furnace-X (SoC) · 中文文档
Anvil-E is the dedicated multimodal embedding series within Vulcan's Anvil AI silicon family, turning the authoritative google/embeddinggemma-2 specification across Text (Anvil-E1), Vision+Text (Anvil-E2), and Audio+Vision+Text (Anvil-E3) into synthesizable 100 MHz+ SystemVerilog RTL with physical Intel Arria 10 GX PCIe Gen3x8 HIL verification.
All next-generation multimodal and edge LLM series (Anvil-EN, Anvil-Edge, Anvil-D, Anvil-QN) are elevated as first-class peer flagship repositories on GitHub AND promoted directly to the top-level root directory of this repository:
| Peer Flagship Series | Standalone GitHub Repository | Top-Level Directories in This Repo | Target Model Family & Key Microarchitecture | STA Fmax & Arria 10 HIL |
|---|---|---|---|---|
| Anvil-E Series | aHappend/anvil-e |
anvil-e1/ · anvil-e2/ · anvil-e3/ · anvil-e4/ |
Gemma-2 / Gemma-3 & embeddinggemma-2 Text/Vision/Audio Trimodal (W4A16 + Q16.16) |
107.31–113.02 MHz · 8-Profile HIL PASSED |
| Anvil-EN Series | aHappend/anvil-en |
anvil-en1/ · anvil-en2/ |
Gemma-4 (E2B/E4B/26B-A4B/31B) 5:1 Hybrid Local/Global KV + Proportional RoPE + PLE (Evolved from Anvil-E4) |
113.02 MHz · 8-Profile HIL PASSED (EN1 PDF · EN2 PDF) |
| Anvil-Edge SoC | aHappend/anvil-e |
anvil-edge/ |
Zero-Host Standalone UART + Hardware UTF-8/BPE Tokenizer + Autoregressive Closed-Loop SoC | 107.42 MHz · 8-Profile & SoC HIL PASSED (Edge PDF) |
| Anvil-D & QN | aHappend/anvil-d · aHappend/anvil-qn |
Peer Flagship LLM Repos | DeepSeek-R1/V3 MLA+MoE & Qwen3/3.5 Hybrid <think> Reasoning |
113.02 MHz · 8-Profile HIL PASSED |
| Gen | Accelerator | Architecture & Numerical Scope | Quartus 17.1 STA (10.0 ns) |
Intel Arria 10 GX Utilization | PCIe Gen3x8 HIL | Academic & Developer Reports |
|---|---|---|---|---|---|---|
| Gen-1 | Anvil-E1 | google/embeddinggemma-2 Text-Only · 24L 5:1 Hybrid GQA · PLE + Matryoshka 768D L2 Norm |
107.31 MHz (WNS +0.681 ns) |
18,420 ALMs (4.31%) · 128 DSPs (8.43%) · 192 M20K |
PASSED (3/3) | Whitepaper PDF · Engineering PDF |
| Gen-2 | Anvil-E2 | google/embeddinggemma-2 Vision+Text · 16L ViT + 3x3 Pooler + 24L Hybrid Backbone |
111.45 MHz (WNS +1.027 ns) |
23,550 ALMs (5.51%) · 192 DSPs (12.65%) · 312 M20K |
PASSED (3/3) | Whitepaper PDF · Engineering PDF |
| Gen-3 | Anvil-E3 | google/embeddinggemma-2 Audio+Vision+Text Trimodal · 12L Conformer + 16L ViT + 24L Backbone |
111.63 MHz (WNS +1.042 ns) |
26,480 ALMs (6.20%) · 224 DSPs (14.76%) · 360 M20K |
PASSED (8/8) | Whitepaper PDF · Engineering PDF |
| Gen-4 | Anvil-E4 | Gemma-3-4B/12B Multimodal Vision-Language + Dual-RoPE + Logit Soft-Capping + Paged KV |
113.02 MHz (WNS +1.152 ns) |
37,255 ALMs (8.72%) · 16 DSPs · 56 M20K |
PASSED (8/8) | Whitepaper PDF · Engineering PDF |
| Peer-EN1 | Anvil-EN1 | Gemma-4 (E2B/E4B) 5:1 Circular Sliding-Window / Global KV + Proportional RoPE + Per-Layer Embeddings (Evolved from Anvil-E4) |
113.02 MHz (WNS +1.152 ns) |
37,255 ALMs (8.72%) · 16 DSPs · 56 M20K |
PASSED (8/8) | Whitepaper PDF · 中文白皮书 · Peer Repo |
| Peer-EN2 | Anvil-EN2 | Gemma-4 Omni-Modal Vision Patch + Audio Conformer + Text Unified PLE & Shared-KV Engine |
113.02 MHz (WNS +1.152 ns) |
37,255 ALMs (8.72%) · 16 DSPs · 56 M20K |
PASSED (8/8) | Whitepaper PDF · 中文白皮书 · Peer Repo |
| Standalone SoC | Anvil-Edge | Zero-Host Edge LLM SoC: Hardware UART + UTF-8/BPE Tokenizer + Vocabulary Detokenizer + Closed-Loop FSM | 107.42 MHz (WNS +0.691 ns) |
39,410 ALMs (9.22%) · 32 DSPs · 96 M20K |
PASSED (8/8) | Whitepaper PDF · 中文白皮书 |
Anvil-E1 · Academic Whitepaper Preview (anvil-e1/SHOWCASE_REPORT.pdf)
 Page 1 · Architecture & KPI Summary |
 Page 2 · Experimental Benchmarks & Parity |
 Page 3 · Arria 10 STA, HIL & Scaling |
Anvil-E2 · Academic Whitepaper Preview (anvil-e2/SHOWCASE_REPORT.pdf)
 Page 1 · Architecture & KPI Summary |
 Page 2 · Experimental Benchmarks & Parity |
 Page 3 · Arria 10 STA, HIL & Scaling |
Anvil-E3 · Academic Whitepaper Preview (anvil-e3/SHOWCASE_REPORT.pdf)
 Page 1 · Architecture & KPI Summary |
 Page 2 · Experimental Benchmarks & Parity |
 Page 3 · Arria 10 STA, HIL & Scaling |
| Silicon Family | Workshop Metaphor | Domain & Series Repositories |
|---|---|---|
| Anvil (Primary Focus) | Heavy forge anvil bearing core compute loads | AI & Large-Model Compute — Anvil-Q (Quantized LLMs) · Anvil-E (Multimodal Embeddings) |
| Billet | Raw metal stock shaped and combined into systems | Digital Signal Processing — Billet-T (FFT/Spectral) · Billet-F (FIR/SOS-IIR Filters) |
| Rivet | Small, critical, rock-solid fasteners | Cryptography & Data Integrity — Rivet-A (AES/GCM/DMA) · Rivet-H (SHA-256/512/HMAC) |
| Swage | Die-forming tool shaping inputs into target forms | Image Processing & ISP — Swage-S (2D Scaler, 3×3 Spatial Filter, Bayer Demosaic, CSC) |
| Bellows | Expanding/contracting continuous airflow | Streaming Data Compression — Bellows-L (LZ4 Decompressor, Hash-Table Compressor, XXH32 DMA) |
| Crucible | Vessel fusing diverse materials into form | Graphics Processing & Rendering — Crucible-G (Triangle Setup, Tile Rasterizer, Z-Buffer & Texture Shader) |
| Furnace | Industrial furnace integrating multiple stages | Heterogeneous SoCs — Furnace-X (Multi-Engine AI + DSP + Crypto + ISP + Compression SoC) |
Author: Sufeng Guo · Microsoft Research Asia · sufeng_guo@smail.nju.edu.cn · MIT License