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Add v8x16.shuffle1 instruction and rename v8x16.shuffle to v8x16.shuffle2_imm #71

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Mar 27, 2019
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Add v8x16.shuffle1 instruction and rename v8x16.shuffle to v8x16.shuffle2_imm #71

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5 changes: 3 additions & 2 deletions proposals/simd/BinarySIMD.md
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Expand Up @@ -23,14 +23,13 @@ instr ::= ...
```

Some SIMD instructions have additional immediate operands following `simdop`.
The `v8x16.shuffle` instruction has 16 bytes after `simdop`.
The `v8x16.shuffle2_imm` instruction has 16 bytes after `simdop`.

| Instruction | `simdop` | Immediate operands |
| --------------------------|---------:|--------------------|
| `v128.load` | `0x00`| m:memarg |
| `v128.store` | `0x01`| m:memarg |
| `v128.const` | `0x02`| i:ImmByte[16] |
| `v8x16.shuffle` | `0x03`| s:LaneIdx32[16] |
| `i8x16.splat` | `0x04`| - |
| `i8x16.extract_lane_s` | `0x05`| i:LaneIdx16 |
| `i8x16.extract_lane_u` | `0x06`| i:LaneIdx16 |
Expand Down Expand Up @@ -167,3 +166,5 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`.
| `f32x4.convert_u/i32x4` | `0xb0`| - |
| `f64x2.convert_s/i64x2` | `0xb1`| - |
| `f64x2.convert_u/i64x2` | `0xb2`| - |
| `v8x16.shuffle1` | `0xc0`| - |
| `v8x16.shuffle2_imm` | `0xc1`| s:LaneIdx32[16] |
25 changes: 22 additions & 3 deletions proposals/simd/SIMD.md
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Expand Up @@ -284,8 +284,8 @@ def S.replace_lane(a, i, x):
The input lane value, `x`, is interpreted the same way as for the splat
instructions. For the `i8` and `i16` lanes, the high bits of `x` are ignored.

### Shuffle lanes
* `v8x16.shuffle(a: v128, b: v128, imm: ImmLaneIdx32[16]) -> v128`
### Shuffling using immediate indices
* `v8x16.shuffle2_imm(a: v128, b: v128, imm: ImmLaneIdx32[16]) -> v128`

Returns a new vector with lanes selected from the lanes of the two input vectors
`a` and `b` specified in the 16 byte wide immediate mode operand `imm`. This
Expand All @@ -294,7 +294,7 @@ return. The indices `i` in range `[0, 15]` select the `i`-th element of `a`. The
indices in range `[16, 31]` select the `i - 16`-th element of `b`.

@gnzlbg gnzlbg Mar 14, 2019

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This should IMO also mention what happens with out-of-range indices (e.g. validation error) for consistency with the variable index shuffle.

@zeux zeux Mar 14, 2019 •
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My understanding was that LaneIdx32 implies that indices must be 0-31. The encoding for these isn't documented atm.

@gnzlbg gnzlbg Mar 14, 2019

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It is not strictly necessary to document these here. The definition of LaneIdx32 states:

[...] Many have a limited valid range, and it is a validation error if the immediate operands are out of range.

ImmLaneIdx32: A byte with values in the range 0–31 identifying a lane.

but I think a "(note: out-of-range indices are a validation error)" might be helpful.

@tlively tlively Mar 14, 2019

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This is not the final spec text, so as long as the intended semantics and opcodes are clear it should be good to go.


```python
def S.shuffle(a, b, s):
def S.shuffle2_imm(a, b, s):
result = S.New()
for i in range(S.Lanes):
if s[i] < S.lanes:
Expand All @@ -304,6 +304,25 @@ def S.shuffle(a, b, s):
return result
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```

### Shuffling using variable indices
* `v8x16.shuffle1(a: v128, s: v128) -> v128`

Returns a new vector with lanes selected from the lanes of the first input
vector `a` specified in the second input vector `s`. The indices `i` in range
`[0, 15]` select the `i`-th element of `a`. For indices outside of the range
the resulting lane is 0.

```python
def S.shuffle1(a, s):
result = S.New()
for i in range(S.Lanes):
if s[i] < S.lanes:
result[i] = a[s[i]]
else:
result[i] = 0
return result
```

## Integer arithmetic

Wrapping integer arithmetic discards the high bits of the result.
Expand Down
4 changes: 2 additions & 2 deletions proposals/simd/TextSIMD.md
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Expand Up @@ -20,8 +20,8 @@ The canonical text format used for printing `v128.const` instructions is
v128.const i32x4 0xNNNNNNNN 0xNNNNNNNN 0xNNNNNNNN 0xNNNNNNNN
```

### v8x16.shuffle
### v8x16.shuffle2_imm

```
v8x16.shuffle i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5
v8x16.shuffle2_imm i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5 i5

@gnzlbg gnzlbg Mar 14, 2019

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This is a bit confusing. These are not really i5s, but they are i8s restricted to the i5 domain.

@gnzlbg gnzlbg Mar 14, 2019

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Maybe this should use LaneIdx32 ?

@zeux zeux Mar 14, 2019

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This is specifying text format so I believe i5 is accurate.

```