Repository navigation
Allow flushing of subnormals in floating point SIMD operations #2
Description
The proposal in #1 includes this text:
An implementation is allowed to flush subnormals in arithmetic floating-point
operations. This means that any subnormal operand is treated as 0, and any
subnormal result is rounded to 0.Note that this differs from WebAssembly scalar floating-point semantics which
require correct subnormal handling.
The issue is also mentioned in the future features design document.
The practical issue for SIMD is 32-bit ARM devices: The ARMv7 ISA has two instruction sets for floating point, VFP and NEON. VFP provides scalar floating point instructions with full support for IEEE 754 subnormal values. NEON provides 64-bit and 128-bit SIMD floating point instructions that only have flush-to-zero semantics for subnormal numbers. The same is true of the AArch32 mode of ARMv8. Only AArch64 supports subnormal values in SIMD instructions.
In summary, if we want to run floating-point SIMD code on 32-bit ARM devices (and 64-bit ARM devices running in 32-bit mode) we need to allow for subnormal values to be flushed to zero.
Activity
jfbastien commentedon Apr 14, 2017
I used to care about this a lot. As time passes it's becoming less and less relevant. I'm not sure SIMD on ARMv7 devices is something we'll need to care about for very long, considering most CPUs are moving to ARMv8. Given this, I think we'd be OK having ARMv7 implementations either scalarize or be non-conformant.
dtig commentedon Dec 14, 2018
As it's been a year since the last discussion, my impression is that we care less about ARMv7 than before, so closing this issue.
sunfishcode commentedon Dec 14, 2018
The currently rendered proposal still contains the text above, permitting implementations to flush. If the intention is to not care about ARMv7, should that text be removed?
dtig commentedon Dec 14, 2018
Text removed in PR #59.