Hyper-V Synthetic Timers and AutoEOI - #855
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Work-in-progress. Currently Windows 11 uses them, doesn't use direct mode yet, but since Hyper-V EOI assist is not implemented results in significantly more EOIs than when using SVM AVIC.
…r and fix fMsgPending even when SINT is masked. Also SIMP enabled and SINT masking doesn't apply in direct-mode.
…led VP assist page/MSR.
Timer message delivery is busted on SMP VMs because timers always fire on last EMT. Also, we should consider MMIO2 mapping of the SIM page after checking large-page issue bugref:7532.
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…P for STIMER messages is done).
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There is a race between Working on fixing that with the current lockfree approach. It requires extending the PIB to hold one more bit per vector for the AutoEOI status but this is more work than initially anticipated and also touches the regular APIC interrupt path more. |
… apicUpdatePendingInterrupts when Hyper-V AutoEOIs are used. Put the AutoEOI state as part of the edge-triggered PIB itself. Use distinct types so edge-triggered and level-sensitive stay distinct.
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Commit To elaborate the race condition: Posting an AutoEOI interrupt made the vector pending in PIB and separately in AutoEOI bitmap. This meant the target EMT can consume and deliver the interrupt with the wrong AutoEOI state in-between and leaving the stale AutoEOI bit which will apply to the next interrupt using the same vector. The APIC PIB (pending interrupt bitmap) was split into edge-triggered and level-sensitive types (since we handle them differently anyway). The edge-triggered bitmap now gains an additional bit for every vector: #define APIC_PIB_INTR_NOT_PENDING 0x0
#define APIC_PIB_INTR_PENDING 0x1
#define APIC_PIB_INTR_PENDING_AUTO_EOI 0x2
#define APIC_PIB_INTR_RSVD 0x3This change means regular APIC code was touched, so it requires as much testing as it can. All the guests I tested continue to work normally but my test setup is very limited. There is still some cleanup I can do in the APIC PIB state/code (e.g. alloc, and removal of some long dead/commented out code) which I deliberately chose not to do here. Can be done later. one of the things I want to check is why the edge-triggered PIB is allocated separately and accessed via "pvApicPibR0", "pvApicPibR3" but level-sensitive PIB we just use the type directly and make it part of the APICCPU structure itself. |
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I'll add fallthrough and will make idxStimer declaration conditional (VBOX_WITH_STATISTICS).
| ++cPending; | ||
| break; | ||
| case APIC_PIB_INTR_RSVD: | ||
| pHlp->pfnPrintf(pHlp, " (%#02x Invalid)", uVector); |
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Needs RT_FALL_THROUGH(); after this line.
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| /* Get the VCPU's synthetic timer config and timer index. */ | ||
| uint64_t const uStimerConfig = pHvStimer->uStimerConfigMsr; | ||
| uint16_t const idxStimer = pHvStimer->idxStimer; |
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idxStimer is never used in release builds without statistics.
…toEOI). ??github:gh-8 github-merge-author:Teknomancer <v.ramshankar@gmail.com>5 svn:sync-xref-src-repo-rev: r175206
svn:sync-xref-src-repo-rev: r175207
svn:sync-xref-src-repo-rev: r175208
svn:sync-xref-src-repo-rev: r175209
svn:sync-xref-src-repo-rev: r175210
…(Hyper-V Synthetic Timers and AutoEOI). github:gh-855 github-merge-author:Teknomancer <v.ramshankar@gmail.com> svn:sync-xref-src-repo-rev: r175211
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Base work for Hyper-V synthetic timers (VP assist page) and AutoEOI.
SMP VMs are still a todo (will R3 release assert).