Building continuous-batching LLM runtimes, Paged KV-cache memory allocators, sub-byte bit-packers, and empirical serving benchmarks from first principles.
Hardware-Calibrated Runtimes · Zero CUDA OOMs · 0ms-Cold-Start Interactive CAD
Empirical roofline modeling, zero-copy physical block gathering, and verified cryptographic provenance.
Portfolio Health: 494 / 494 tests passed (100% pass rate) across 8 core repositories.
All studios are deployed as permanent, zero-cold-start static web applications on Hugging Face Spaces (sdk: static) with interactive client-side execution:
| Studio | Space Link | Interactive Capabilities |
|---|---|---|
token-atlas |
prajwalpujari16/token-atlas | Multilingual Token Inflation Tax Explorer: 52-language FLORES-200 inflation matrix & token fertility multipliers across 6 major tokenizers (GPT-4o, LLaMA-3, Claude, Qwen, DeepSeek, Gemma). |
infersize |
prajwalpujari16/infersize | LLM Capacity Planning CAD: Pre-flight analytical VRAM sizing, multi-GPU comparison matrix, speculative decoding latency sizer, and cloud TCO ($/1M tokens) estimator. |
quantbench |
prajwalpujari16/quantbench | Sub-Byte Quantization Studio: SQNR-vs-compression Pareto frontier explorer, live BitNet 1.58b / INT4 / 2:4 sparsity bit-packing registers, and Transformer layer sensitivity simulator. |
sched-sim |
prajwalpujari16/sched-sim |
Discrete-Event Serving Scheduler: Animated Gantt player demonstrating Head-of-Line prefill blocking vs. Sarathi Chunked Prefill ( |
mini-infer |
prajwalpujari16/mini-infer | PagedAttention GPU Memory Pool: Interactive virtual block table allocator, copy-on-write radix prefix caching simulator, and speculative decoding acceptance verifier. |
runsonmine |
prajwalpujari16/runsonmine |
Empirical Silicon LLM Benchmark Registry: 24 physical measurements on Dual Tesla T4 & RTX 3050 Laptop, concurrency scaling curves ( |
| Dataset | Hub Link | Verified Contents |
|---|---|---|
token-atlas-benchmark |
prajwalpujari16/token-atlas-benchmark | 52-language FLORES-200 benchmark & token inflation metrics across tokenizers. |
quantbench-pareto |
prajwalpujari16/quantbench-pareto | 12-configuration Pareto frontier + 28 layer sensitivity rows. |
llm-serving-traces |
prajwalpujari16/llm-serving-traces | 165 real serving traces (LMSYS/RAG/CodeGen) + 15 scheduler comparisons + 12 silicon validation rows. |
consumer-silicon-benchmarks |
prajwalpujari16/consumer-silicon-benchmarks | 24 empirical data points on Dual Tesla T4 & RTX 3050 Laptop + 6-step concurrency curve. |
# 1. Profile local server capacity (Ollama, vLLM, llama.cpp) with automated roofline tuning
pip install servebench && servebench quick
# 2. Pre-flight analytical capacity planning, multi-GPU matrix & cloud $/1M tokens (zero GPU needed)
pip install infersize && infersize compare --model qwen2.5-7b --quant fp16
# 3. Continuous-batching inference runtime with Paged KV-cache (pure PyTorch, zero C++ build steps)
pip install mini-infer
# 4. Discrete-event serving simulator with Radix prefix caching & chunked prefill
pip install sched-sim && sched-sim run --scheduler chunked --chunk-budget 512
# 5. From-scratch quantization engine & Pareto evaluation benchmark (INT4/INT8/FP8/BitNet 1.58b)
pip install quantbench-engine && quantbench pack-inspect --format int4
# 6. Multilingual token inflation tax analyzer across 52 languages
pip install token-atlas && token-atlas compare --text "Hello world"| Flagship | Core Architecture | Empirical Silicon Numbers | Release & Provenance |
|---|---|---|---|
| mini-infer | Lightweight continuous-batching LLM runtime in pure PyTorch for Qwen2.5. Iteration-level dynamic scheduler, Paged KV-cache with dynamic sub-byte INT4/FP8 compression (-72.7% VRAM), radix prefix caching, and Leviathan speculative verifier. | • 27.0 tok/s at c=4 (+130.8%) • 2.04 Tok/Joule (13.2 W) • -72.7% KV-cache VRAM (INT4) • 68/68 tests pass (100%) |
|
| servebench | LLM serving capacity load-tester & auto-tuning harness (servebench tune). Multi-trial repeats with 95% CIs and synchronized NVML GPU telemetry. |
• Honest p99 ( • MBU roofline profiling • Slot/Queue/Bandwidth diagnostics • 169/169 tests pass (100%) |
|
| quantbench | Unified from-scratch quantization engine (INT4/INT8/FP8/BitNet 1.58b), vectorized sub-byte packing, Ampere 2:4 structured sparsity, dynamic QuantLinear layers, and dual-metric Pareto evaluation benchmark. |
• 3.5x INT4 / 7.5x BitNet • 0-copy hook dequant • 53/53 tests pass (95% cov) |
|
| sched-sim | Discrete-event LLM serving simulator with first-principles roofline latency models, SGLang-style Radix prefix caching, Sarathi chunked prefill, and Perfetto trace visualizer. | • <4.8% silicon error • 0.87s full sweep • 45/45 tests pass (87% cov) |
|
| infersize | Pre-flight analytical performance modeling, multi-GPU comparison matrix, speculative decoding sizer, and cloud TCO ($/1M tokens) capacity planner. Interactive Web Studio, NVML hardware fit verifier, and dynamic Hugging Face Hub ingestion. | • <10 ms CPU solve • 60/60 tests pass (89% cov) • Zero GPU required |
|
| token-atlas | Multilingual token inflation tax visualizer and cost calculator across 52 world languages and 6 foundation tokenizers. | • 52 languages analyzed • 24/24 tests pass (100%) • 0ms static runtime |
|
| runsonmine | Community database of measured (not estimated) LLM inference speeds on real consumer silicon (laptops, desktops, Macs). | • 24 empirical runs • 24/24 tests pass (100%) • 100% SLA attainment |
|
| EdgeSLM | Air-gapped document sensitivity classifier and Tier-1 DLP secret scanner for edge CPU inference. | • 20+ HF downloads (v3) • 6.7× dynamic batching • 51/51 tests pass (100%) |
|
I believe that engineering credibility is built by documenting trade-offs, architectural failures, and hardware bounds alongside performance gains:
-
Naive KV-Allocation Fails Under Dynamic Lengths:
Pre-allocating contiguous tensor buffers for worst-case context lengths wasted >60% of GPU memory due to internal and external fragmentation. Fixed by implementing fixed 16-token physical block pools with virtual-to-physical block tables in pure PyTorch, cutting memory waste to <3.8%. -
Unbatched Iteration Bottlenecks on DRAM Memory Bandwidth:
Stepping concurrent sequences through serial model calls forced the GPU to stream model weights from DRAM 4 separate times per step (capping decode at 11.7 tok/s on an RTX 3050). Switching to zero-copy physical block gathering streams weights exactly once per step across all sequences, jumping throughput to 27.0 tok/s (+130.8%) and delivering 2.04 Tok/Joule. -
Head-of-Line Prefill Starvation Under Continuous Batching:
In standard FCFS continuous batching, a 2,048-token prompt prefill monopolizes the compute pipeline for >120ms, causing active decoding streams to stutter with severe TPOT latency spikes. Validated throughsched-simthat Sarathi-style Chunked Prefill ($C=512$ ) interleaves prompt chunks with decodes, keeping TPOT under 40ms without hurting throughput. -
Transformer Layer Quantization Sensitivity Asymmetry:
Attention Query ($W_q$ ) and Key ($W_k$ ) projections suffer 1.8–2.4 dB greater SQNR degradation under low-bit quantization than feed-forward MLP layers because phase drift in the attention dot-product$QK^T / \sqrt{d_k}$ propagates exponentially through softmax. Demonstrated inquantbenchthat keeping$W_q, W_k$ , and$W_{\text{down}}$ in higher precision or finer group size ($G=32$ ) yields near-FP16 perplexity while compressing MLP Gate and Up into aggressive sub-byte formats. -
No Cherry-Picked Latency Metrics:
Single-run p99 latency spikes are statistically deceptive without sufficient sample size.servebenchstrictly enforces$N \ge 100$ before calculating p99 percentiles, and reports 95% confidence intervals across multi-trial repeats.
- Roofline Benchmarking & Auto-Tuning LLM Serving: How We Pushed Pure PyTorch to 27 tok/s (
2026-10-23)
Measuring empirical Memory Bandwidth Utilization (MBU), saturation knees, and multi-stream batching to eliminate TTFT degradation on consumer laptop GPUs. - Why Naive KV-Caches Waste >60% VRAM (And How Paged Memory Fixes It) (
2026-10-22)
How replacing contiguous memory allocations with 16-token physical blocks and virtual table mapping brings production PagedAttention to pure PyTorch.
Runtime Systems : Paged KV-Cache Allocators · Continuous Batching · Radix Prefix Caching · Speculative Decoding · Discrete-Event Simulation
Silicon Profiling : Roofline MBU Modeling · NVML Telemetry · Saturation Knee Detection · TTFT / ITL / TPOT Analysis
Core Stack : PyTorch (SDPA, Tensor Gathers) · Python 3.10+ · CUDA / NVML · ONNX Runtime INT4 · Hugging Face
Quantization : Symmetric AbsMax · INT4 Blockwise · BitNet 1.58b Ternary · Ampere 2:4 Structured Sparsity · SmoothQuant · AWQ / GPTQ
Serving & Infra : FastAPI · Asyncio / Aiohttp · SSE Streaming · vLLM · Ollama · Docker · GitHub Actions CI/CD
Security & Trust : PyPI Trusted Publishers (OIDC) · Sigstore Cryptographic Attestation · Zero-Secret Airgap DLP
- Portfolio Website: prajwal-pujari.vercel.app
- Hugging Face Hub: huggingface.co/prajwalpujari16
- PyPI Packages: pypi.org/user/Prajwal2002PI
- LinkedIn: linkedin.com/in/prajwal-pujari-mn9964
- Email: prajwalpujari16@gmail.com


