arm: hisilicon: add hi3520dv200 SoC support (DT + mach-hibvt, L2, SATA, SFC), tested on hardware

Documentation/devicetree/bindings/ata/hisilicon,hi3520dv200-ahci.yaml

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/hisilicon,hi3520dv200-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Hi3520DV200 AHCI SATA controller
+
+maintainers:
+  - Bjorn Stout <bjorn.stout@hotmail.com>
+
+description:
+  The Hi3520DV200's two-port AHCI controller. Its PHYs are clocked, taken
+  out of reset and programmed by the driver through the SoC's SATA
+  clock/reset register (PERI_CRG45) before the AHCI core is started.
+
+properties:
+  compatible:
+    const: hisilicon,hi3520dv200-ahci
+
+  reg:
+    items:
+      - description: AHCI registers, including the vendor PHY registers
+      - description: PERI_CRG45, the SATA clock and reset register
+
+  interrupts:
+    maxItems: 1
+
+  hisilicon,phy-config:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Value for the per-port PHY control register (port offset 0x74).
+      HiSilicon's Hi3520D reference value, 0x0e276756, is the default.
+      XiongMai boards need 0x0e262709, the value their vendor firmware
+      writes; with the default their link keeps resetting.
+    default: 0x0e276756
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    sata@10080000 {
+        compatible = "hisilicon,hi3520dv200-ahci";
+        reg = <0x10080000 0x10000>, <0x200300b4 0x4>;
+        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+        hisilicon,phy-config = <0x0e262709>;
+    };

Documentation/devicetree/bindings/cache/hisilicon,hi3520dv200-l2cache.yaml

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/hisilicon,hi3520dv200-l2cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Hi3520DV200 L2 cache controller (hil2v200)
+
+maintainers:
+  - Bjorn Stout <bjorn.stout@hotmail.com>
+
+description:
+  HiSilicon's own outer cache controller in the Hi3520DV200, 128 KB with
+  8 ways and 32-byte lines. It is not an ARM PL310 (its ID register reads 0)
+  and is maintained by address, by way and set, or a whole way at a time.
+
+allOf:
+  - $ref: /schemas/cache-controller.yaml#
+
+properties:
+  compatible:
+    const: hisilicon,hi3520dv200-l2cache
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: check 0 (error) interrupt
+      - description: check 1 (error) interrupt
+      - description: combined interrupt
+
+  cache-unified: true
+
+  cache-level:
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - cache-unified
+  - cache-level
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    cache-controller@20700000 {
+        compatible = "hisilicon,hi3520dv200-l2cache";
+        reg = <0x20700000 0x10000>;
+        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+        cache-unified;
+        cache-level = <2>;
+    };

Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt

@@ -1,8 +1,11 @@
 Hisilicon Fast Ethernet MDIO Controller interface
 
 Required properties:
-- compatible: should be "hisilicon,hisi-femac-mdio".
-- reg: address and length of the register set for the device.
+- compatible: should be "hisilicon,hisi-femac-mdio", or
+  "hisilicon,hi3520dv200-femac-mdio" followed by "hisilicon,hisi-femac-mdio".
+- reg: address and length of the register set for the device. On
+  "hisilicon,hi3520dv200-femac-mdio" a second entry gives the internal PHY
+  control register, whose low five bits set the address the PHY answers at.
 - clocks: A phandle to the reference clock for this device.
 
 - PHY subnode: inherits from phy binding [1]

Documentation/devicetree/bindings/spi/hisilicon,hi3520dv200-sfc.yaml

@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/hisilicon,hi3520dv200-sfc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Hi3520DV200 SPI flash controller (SFC v350)
+
+maintainers:
+  - Bjorn Stout <bjorn.stout@hotmail.com>
+
+description:
+  The SPI-NOR controller of the Hi3520DV200 (hardware version 0x350), with
+  the register layout of the v3xx controllers handled by spi-hisi-sfc-v3xx.
+  Without an interrupt the driver polls for completion.
+
+allOf:
+  - $ref: spi-controller.yaml#
+
+properties:
+  compatible:
+    const: hisilicon,hi3520dv200-sfc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  num-cs:
+    description:
+      Number of chip selects. The flash on Hi3520DV200 boards is on CS1.
+    maximum: 2
+    default: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    spi@10010000 {
+        compatible = "hisilicon,hi3520dv200-sfc";
+        reg = <0x10010000 0x1000>;
+        num-cs = <2>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        flash@1 {
+            compatible = "jedec,spi-nor";
+            reg = <1>;
+            label = "hi_sfc";
+            spi-max-frequency = <50000000>;
+        };
+    };

arch/arm/boot/dts/hisilicon/Makefile

@@ -26,5 +26,7 @@ dtb-$(CONFIG_ARCH_HI3516CV100) += \
 	hi3516cv100-demb.dtb
 dtb-$(CONFIG_ARCH_HI3516AV100) += \
 	hi3516av100-demb.dtb
+dtb-$(CONFIG_ARCH_HI3520DV200) += \
+	hi3520dv200-nbd6808t.dtb
 dtb-$(CONFIG_ARCH_HI3519V101) += \
 	hi3519v101-demb.dtb

arch/arm/boot/dts/hisilicon/hi3520dv200-nbd6808t.dts

@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * XiongMai NBD6808T-PL NVR (MBD0157 board), Hi3520DV200, 8 MB SPI NOR.
+ */
+
+/dts-v1/;
+#include "hi3520dv200.dtsi"
+
+/ {
+	model = "XiongMai NBD6808T-PL (Hi3520DV200)";
+	compatible = "xiongmai,nbd6808t-pl", "hisilicon,hi3520dv200";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	/*
+	 * 256 MB of DDR. The vendor firmware gave Linux the first 128 MB and
+	 * the rest to the media memory zone; without the MPP all of it is
+	 * ordinary memory except the VGA framebuffer reserved below.
+	 */
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		vga_fb_mem: framebuffer@8f000000 {
+			reg = <0x8f000000 0x400000>;
+			no-map;
+		};
+	};
+
+	/*
+	 * VGA, 1920x1080@60. The vendor bootloader drives the display
+	 * controller ("startvo 0 4 10; startgx 0 0x8f000000 3840 0 0 1920
+	 * 1080" opens VGA at 1080p60 and graphics layer 0 at this buffer,
+	 * scanned out as ARGB1555 with the alpha bit ignored); Linux only
+	 * draws into it. Without those bootloader commands nothing is shown.
+	 */
+	framebuffer@8f000000 {
+		compatible = "simple-framebuffer";
+		reg = <0x8f000000 0x3f4800>;
+		memory-region = <&vga_fb_mem>;
+		width = <1920>;
+		height = <1080>;
+		stride = <3840>;
+		format = "x1r5g5b5";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+/* The RJ45 is on the up port, through the SoC's internal PHY at address 3. */
+&mdio {
+	status = "okay";
+
+	phy_up: ethernet-phy@3 {
+		reg = <3>;
+	};
+};
+
+&eth_up {
+	phy-handle = <&phy_up>;
+	phy-mode = "mii";
+	status = "okay";
+};
+
+/*
+ * 8 MB MX25L6406E on CS1. The partitions below are the stock firmware's
+ * layout, read-only; they only apply when the bootloader passes no
+ * "mtdparts=hi_sfc:..." of its own.
+ */
+&sfc {
+	status = "okay";
+
+	flash@1 {
+		compatible = "jedec,spi-nor";
+		reg = <1>;
+		/* the name both the vendor and OpenIPC bootloaders use in mtdparts= */
+		label = "hi_sfc";
+		spi-max-frequency = <50000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot";
+				reg = <0x000000 0x030000>;
+				read-only;
+			};
+			partition@30000 {
+				label = "romfs";
+				reg = <0x030000 0x1f0000>;
+				read-only;
+			};
+			partition@220000 {
+				label = "usr";
+				reg = <0x220000 0x3b0000>;
+				read-only;
+			};
+			partition@5d0000 {
+				label = "custom";
+				reg = <0x5d0000 0x1a0000>;
+				read-only;
+			};
+			partition@770000 {
+				label = "logo";
+				reg = <0x770000 0x010000>;
+				read-only;
+			};
+			partition@780000 {
+				label = "mtd";
+				reg = <0x780000 0x080000>;
+				read-only;
+			};
+			/* the whole chip, for verifying it against a backup */
+			partition@0-all {
+				label = "all";
+				reg = <0x000000 0x800000>;
+				read-only;
+			};
+		};
+	};
+};
+
+/*
+ * The vendor firmware's PHY value; with the Hi3520D reference one this
+ * board's link keeps resetting.
+ */
+&sata {
+	hisilicon,phy-config = <0x0e262709>;
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&ehci {
+	status = "okay";
+};