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ArpitP777/README.md

👨‍💻 About Me

Hi, I'm Arpit Prakash 👋

ECE Undergraduate @ BIT Mesra | Aspiring RTL Design & Verification Engineer

I’m a third-year Electronics and Communication Engineering student passionate about VLSI, ASIC design verification, and digital system design. I build hands-on projects using Verilog and SystemVerilog.

  • Currently strengthening my RTL design and verification skills
  • Exploring ASIC design flow and semiconductor technologies
  • Interested in digital design, verification and hardware–software integration
  • Open to learning, collaboration, and VLSI/RTL internship opportunities

Skills & Tools

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  1. Single-Cycle-RISC-V-Processor-RV32I-ISA Single-Cycle-RISC-V-Processor-RV32I-ISA Public

    Making a single cycle RISC V processor based on standard RV32I format for low power, efficient usage.

    Verilog 1

  2. Vending-Machine-Verilog Vending-Machine-Verilog Public

    Built a FSM vending machine in Verilog supporting multi-item pricing, coin inputs, dispensing control, and change return logic.

    Verilog 2

  3. UART_v1 UART_v1 Public

    A Verilog-based FPGA UART transmitter that sends 8-bit, LSB-first serial data using standard 8-N-1 framing, configurable baud timing, and a simulation testbench.

    Verilog 1

  4. SPI_v1 SPI_v1 Public

    An FPGA-based, 8-bit SPI master implemented in Verilog, featuring MSB-first full-duplex communication, clock generation, and a SystemVerilog testbench for simulation.

    Verilog 1