From 56eb8c264abd96585c1333d0e82e8ed4bc36c6fa Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Fri, 22 Sep 2023 10:10:36 +0200 Subject: [PATCH 1/5] platform: posix: clk: add lowest freq index This patch adds CPU_LOWEST_FREQ_IDX definition to keep compliance with changes in base_fw. Signed-off-by: Tomasz Leman --- src/platform/posix/include/platform/lib/clk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/platform/posix/include/platform/lib/clk.h b/src/platform/posix/include/platform/lib/clk.h index 3c9ff3b96950..7d396330a0cb 100644 --- a/src/platform/posix/include/platform/lib/clk.h +++ b/src/platform/posix/include/platform/lib/clk.h @@ -5,6 +5,7 @@ #define CLK_MAX_CPU_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC #define CPU_LPRO_FREQ_IDX 1 +#define CPU_LOWEST_FREQ_IDX CPU_LPRO_FREQ_IDX /* This is not a platform function, it's defined in src/lib/clk.c. * But the declaration has historically been in the platform layer, so From ef28f9a658d8b36d992e2a0db0dfa1a64749056c Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Thu, 14 Sep 2023 14:22:57 +0200 Subject: [PATCH 2/5] base_fw: get fw config This patch is changing value of slow clock in response for FwConfigGet from LP clock to the lowest clock is section "slow clock". Signed-off-by: Tomasz Leman --- src/audio/base_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/audio/base_fw.c b/src/audio/base_fw.c index 05e99194e608..ce7b5ca7778e 100644 --- a/src/audio/base_fw.c +++ b/src/audio/base_fw.c @@ -51,7 +51,7 @@ static int basefw_config(uint32_t *data_offset, char *data) tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG, - clock_get_freq(CPU_LPRO_FREQ_IDX)); + clock_get_freq(CPU_LOWEST_FREQ_IDX)); tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG, IPC4_ALH_CAVS_1_8); From a619d320f1fb451dca695e3616aab39d277479c1 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Wed, 6 Sep 2023 15:34:39 +0200 Subject: [PATCH 3/5] ace: clock: update clock definitions ACE_1.5 and ACE_2.0 use only two clocks for DSP cores. First is WOVRCO and second is ACE IPLL. IPLL allows to configure it to work like LP RING Oscillator Clock or HP RING Oscillator Clock. Currently, the driver does not allow this, so I remove the frequency that cannot be achieved anyway. Clocks frequencies: WOV: 38.4 MHz IPLL: 393.216 MHz Signed-off-by: Tomasz Leman --- src/platform/lunarlake/include/platform/lib/clk.h | 10 ++++------ src/platform/lunarlake/lib/clk.c | 5 ++--- src/platform/meteorlake/include/platform/lib/clk.h | 10 ++++------ src/platform/meteorlake/lib/clk.c | 5 ++--- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/src/platform/lunarlake/include/platform/lib/clk.h b/src/platform/lunarlake/include/platform/lib/clk.h index fe8f140ff0a6..77e72d8c6ccd 100644 --- a/src/platform/lunarlake/include/platform/lib/clk.h +++ b/src/platform/lunarlake/include/platform/lib/clk.h @@ -14,21 +14,19 @@ #include -#define CLK_MAX_CPU_HZ 400000000 +#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ #define CPU_WOVCRO_FREQ_IDX 0 -#define CPU_LPRO_FREQ_IDX 1 - -#define CPU_HPRO_FREQ_IDX 2 +#define CPU_IPLL_FREQ_IDX 1 #define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX -#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX +#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX #define SSP_DEFAULT_IDX 1 -#define NUM_CPU_FREQ 3 +#define NUM_CPU_FREQ 2 #define NUM_SSP_FREQ 3 diff --git a/src/platform/lunarlake/lib/clk.c b/src/platform/lunarlake/lib/clk.c index ed2936b5efc4..7ad664c94118 100644 --- a/src/platform/lunarlake/lib/clk.c +++ b/src/platform/lunarlake/lib/clk.c @@ -9,9 +9,8 @@ #include static const struct freq_table platform_cpu_freq[] = { - { 38400000, 38400 }, - { 120000000, 120000 }, - { CLK_MAX_CPU_HZ, 400000 }, + { CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 }, + { CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 }, }; STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies); diff --git a/src/platform/meteorlake/include/platform/lib/clk.h b/src/platform/meteorlake/include/platform/lib/clk.h index 2eb1732aad55..fec0a582ab7e 100644 --- a/src/platform/meteorlake/include/platform/lib/clk.h +++ b/src/platform/meteorlake/include/platform/lib/clk.h @@ -14,21 +14,19 @@ #include -#define CLK_MAX_CPU_HZ 400000000 +#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ #define CPU_WOVCRO_FREQ_IDX 0 -#define CPU_LPRO_FREQ_IDX 1 - -#define CPU_HPRO_FREQ_IDX 2 +#define CPU_IPLL_FREQ_IDX 1 #define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX -#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX +#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX #define SSP_DEFAULT_IDX 1 -#define NUM_CPU_FREQ 3 +#define NUM_CPU_FREQ 2 #define NUM_SSP_FREQ 3 diff --git a/src/platform/meteorlake/lib/clk.c b/src/platform/meteorlake/lib/clk.c index 227bc9fd9366..20221b89d790 100644 --- a/src/platform/meteorlake/lib/clk.c +++ b/src/platform/meteorlake/lib/clk.c @@ -9,9 +9,8 @@ #include static const struct freq_table platform_cpu_freq[] = { - { 38400000, 38400 }, - { 120000000, 120000 }, - { CLK_MAX_CPU_HZ, 400000 }, + { CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 }, + { CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 }, }; STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies); From 76eea44febc404d2817557f8500dc461b18eb517 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Wed, 6 Sep 2023 16:04:43 +0200 Subject: [PATCH 4/5] ace: overlay: update clock frequency Changing max clock frequency for FPGA configuration. Signed-off-by: Tomasz Leman --- app/overlays/lnl/fpga_overlay.conf | 1 + app/overlays/mtl/fpga_overlay.conf | 1 + 2 files changed, 2 insertions(+) diff --git a/app/overlays/lnl/fpga_overlay.conf b/app/overlays/lnl/fpga_overlay.conf index 0fc3ac375789..eebbfee72648 100644 --- a/app/overlays/lnl/fpga_overlay.conf +++ b/app/overlays/lnl/fpga_overlay.conf @@ -1,2 +1,3 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 CONFIG_DAI_DMIC_HW_IOCLK=19200000 +CONFIG_XTENSA_CCOUNT_HZ=40000000 diff --git a/app/overlays/mtl/fpga_overlay.conf b/app/overlays/mtl/fpga_overlay.conf index 0fc3ac375789..eebbfee72648 100644 --- a/app/overlays/mtl/fpga_overlay.conf +++ b/app/overlays/mtl/fpga_overlay.conf @@ -1,2 +1,3 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 CONFIG_DAI_DMIC_HW_IOCLK=19200000 +CONFIG_XTENSA_CCOUNT_HZ=40000000 From 9fe10d2ad7601404709eee6655e5fb1c7f81f525 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Tue, 26 Sep 2023 23:21:43 +0200 Subject: [PATCH 5/5] west.yml: update zephyr to b2f7ea0523 Zepych update: total of 736 commits. 492517b918 west.yml: Update NXP HAL SDK to 2.14 a5d1fd9857 soc: adsp: clk: update clock switch flow 9656056b19 dts: adsp: ace20: remove lp clock 50f0e223e8 dts: adsp: ace15: remove lp clock cf6d5f95b6 adsp: clk: ace: select ipll if wovrco is unavailable 2d835e1b29 dts: adsp: ace20: replace hp with ipll clock dcecda859c dts: adsp: ace15: replace hp with ipll clock 2f2689e3d3 intel_adsp: ace15: shim: update wovrco request bit ea9dd59460 yamllint: bindings: add ipll clock index 1ddabfa8d8 dai: intel: dmic: fix shadow variable b26921d776 dai: intel: dmic: New functions for writing fir coefficients cba9ec10c3 dai: intel: tgl: dmic: Refactor of dai_nhlt_dmic_dai_params_get function c28e8ba9ba dai: intel: dmic: Add pdm_base and pdm_idx variables in blob parser 2452aaad50 dai: intel: dmic: Separate fir configuration code into function f74fd8edaf dai: intel: ace: dmic: Add dai_dmic_start_fifo_packers function 76d03e798f dai: intel: ace: dmic: Using the WAIT_FOR macro in waiting functions 3fbaed4de9 dai: intel: ace: dmic: Refactor of dai_nhlt_dmic_dai_params_get function d7672af838 dai: intel: dmic: Combine PDM registers definitions 8ea53d49b6 dai: intel: dmic: nhlt: Move debug print code to a separate functions 81944c5c62 dai: intel: dmic: Move definitions of nhlt structures to a new file Signed-off-by: Tomasz Leman --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 5f4db594af5d..8543b993e2b1 100644 --- a/west.yml +++ b/west.yml @@ -45,7 +45,7 @@ manifest: - name: zephyr repo-path: zephyr - revision: 2f90ef488a4e97c94c2cc5b95dacd1b15de32216 + revision: 492517b918d267f553688cd6b9d59b92ffc10f91 remote: zephyrproject # Import some projects listed in zephyr/west.yml@revision