From 697f5bcb1682d7fa1c84f094213852b73f44a087 Mon Sep 17 00:00:00 2001 From: Fred Oh Date: Thu, 2 Apr 2020 11:06:49 -0700 Subject: [PATCH 1/2] topology: add macro to support eq filters for sof-cml-rt5682 The patch shows a proposal how to propagate pipeline filter coefficients data definition at topology top level. It is an useful way to avoid to create different new pipeline macros for different filter. Define filter coefficients data with macro DEF_EQFIR_PRIV and DEF_EQFIR_COEF, which will be replaced unique name by adding PIPELINE number. For IIR filter, equivalent macro is DEF_EQIIR_PRIV and DEF_EQIIR_COEF. Makefile define each pipeline processing HSEARPROC, HSMICRPOC, SPKPROC, DMICPROC etc. Each variable should support default value to minimize current topologies. When new filter blob is required, define PIPELINE_FILTERx in makefile. This method provides more flexible way to support variable number of filters in the pipeline. The other clean up for topology macros include definions for unique volume tokens and unique filter coefficient definitions. Signed-off-by: Fred Oh --- tools/topology/CMakeLists.txt | 3 + tools/topology/m4/eq_fir_coef_flat.m4 | 2 +- tools/topology/m4/eq_iir_coef_flat.m4 | 2 +- .../m4/eq_iir_coef_highpass_20hz_0db_16khz.m4 | 2 +- .../m4/eq_iir_coef_highpass_20hz_0db_48khz.m4 | 2 +- .../eq_iir_coef_highpass_20hz_20db_16khz.m4 | 2 +- .../eq_iir_coef_highpass_20hz_20db_48khz.m4 | 2 +- .../m4/eq_iir_coef_highpass_30hz_0db_16khz.m4 | 2 +- .../m4/eq_iir_coef_highpass_30hz_0db_48khz.m4 | 2 +- .../eq_iir_coef_highpass_30hz_20db_16khz.m4 | 2 +- .../eq_iir_coef_highpass_30hz_20db_48khz.m4 | 2 +- .../m4/eq_iir_coef_highpass_40hz_0db_16khz.m4 | 2 +- .../m4/eq_iir_coef_highpass_40hz_0db_48khz.m4 | 2 +- .../eq_iir_coef_highpass_40hz_20db_16khz.m4 | 2 +- .../eq_iir_coef_highpass_40hz_20db_48khz.m4 | 2 +- .../m4/eq_iir_coef_highpass_50hz_0db_16khz.m4 | 2 +- .../m4/eq_iir_coef_highpass_50hz_0db_48khz.m4 | 2 +- .../eq_iir_coef_highpass_50hz_20db_16khz.m4 | 2 +- .../eq_iir_coef_highpass_50hz_20db_48khz.m4 | 2 +- tools/topology/sof-cml-rt5682.m4 | 21 ++- tools/topology/sof/pipe-eq-fir-capture.m4 | 12 +- tools/topology/sof/pipe-eq-fir-playback.m4 | 12 +- .../sof/pipe-eq-fir-volume-capture.m4 | 129 ++++++++++++++++++ .../sof/pipe-eq-fir-volume-playback.m4 | 23 +++- tools/topology/sof/pipe-eq-iir-capture.m4 | 19 ++- tools/topology/sof/pipe-eq-iir-playback.m4 | 12 +- .../sof/pipe-eq-iir-volume-playback.m4 | 30 ++-- tools/topology/sof/pipe-highpass-capture.m4 | 32 +++-- .../sof/pipe-highpass-switch-capture.m4 | 31 +++-- 29 files changed, 279 insertions(+), 81 deletions(-) create mode 100644 tools/topology/sof/pipe-eq-fir-volume-capture.m4 diff --git a/tools/topology/CMakeLists.txt b/tools/topology/CMakeLists.txt index 527add567d1b..73e2d1859dad 100644 --- a/tools/topology/CMakeLists.txt +++ b/tools/topology/CMakeLists.txt @@ -98,6 +98,9 @@ set(TPLGS "sof-apl-asrc-pcm512x\;sof-apl-asrc-pcm512x" "sof-apl-src-pcm512x\;sof-apl-src-pcm512x" "sof-cml-rt5682\;sof-cml-rt5682\;-DPLATFORM=cml" + "sof-cml-rt5682\;sof-cml-eq-fir-rt5682\;-DPLATFORM=cml\;-DHSMICPROC=eq-fir-volume" + "sof-cml-rt5682\;sof-cml-eq-fir-loud-rt5682\;-DPLATFORM=cml\;-DHSMICPROC=eq-fir-volume\;-DPIPELINE_FILTER1=eq_fir_coef_loudness.m4" + "sof-cml-rt5682\;sof-cml-eq-iir-rt5682\;-DPLATFORM=cml\;-DHSEARPROC=eq-iir-volume" "sof-cml-rt5682\;sof-whl-rt5682\;-DPLATFORM=whl" "sof-cml-rt5682\;sof-icl-rt5682\;-DPLATFORM=icl" "sof-cml-rt5682-kwd\;sof-cml-rt5682-kwd\;-DPLATFORM=cml" diff --git a/tools/topology/m4/eq_fir_coef_flat.m4 b/tools/topology/m4/eq_fir_coef_flat.m4 index a8f4119d11af..badad66dfecb 100644 --- a/tools/topology/m4/eq_fir_coef_flat.m4 +++ b/tools/topology/m4/eq_fir_coef_flat.m4 @@ -1,5 +1,5 @@ # Flat FIR EQ 19-Dec-2018 -CONTROLBYTES_PRIV(EQFIR_priv, +CONTROLBYTES_PRIV(DEF_EQFIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_flat.m4 b/tools/topology/m4/eq_iir_coef_flat.m4 index 72e104f3d0e3..4c01a5bc39ed 100644 --- a/tools/topology/m4/eq_iir_coef_flat.m4 +++ b/tools/topology/m4/eq_iir_coef_flat.m4 @@ -1,5 +1,5 @@ # Flat IIR EQ 18-Dec-2018 -CONTROLBYTES_PRIV(EQIIR_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0x00,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_16khz.m4 index cb1fd5451898..17d5cab0d8db 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_16khz.m4 @@ -1,5 +1,5 @@ # 20 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP20HZ0dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_48khz.m4 index 669c9f3483b8..176759a2f1e7 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_20hz_0db_48khz.m4 @@ -1,5 +1,5 @@ # 20 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP20HZ0dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_16khz.m4 index a0dc498f8893..b5b6f6e5eb86 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_16khz.m4 @@ -1,5 +1,5 @@ # 20 Hz second order high-pass, gain 20 dB, created with example_iir_eq.m 30-Mar-2020 -CONTROLBYTES_PRIV(EQIIR_HP20HZ20dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xe0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_48khz.m4 index ea8786268b95..5b884ce9b812 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_20hz_20db_48khz.m4 @@ -1,5 +1,5 @@ # 20 Hz second order high-pass, gain 20 dB, created with example_iir_eq.m 30-Mar-2020 -CONTROLBYTES_PRIV(EQIIR_HP20HZ20dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xe0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_16khz.m4 index 03be97e82651..ea3ab034819b 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_16khz.m4 @@ -1,5 +1,5 @@ # 30 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP30HZ0dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_48khz.m4 index a77770b613ac..198fc603e805 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_30hz_0db_48khz.m4 @@ -1,5 +1,5 @@ # 30 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP30HZ0dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_16khz.m4 index 5469d1e59f1f..a343371053e4 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_16khz.m4 @@ -1,5 +1,5 @@ # 30 Hz second order high-pass, gain 20 dB, created with example_iir_eq.m 30-Mar-2020 -CONTROLBYTES_PRIV(EQIIR_HP30HZ20dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xe0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_48khz.m4 index 940eb6ca2781..f0fda06be825 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_30hz_20db_48khz.m4 @@ -1,5 +1,5 @@ # 30 Hz second order high-pass, gain 20 dB, created with example_iir_eq.m 30-Mar-2020 -CONTROLBYTES_PRIV(EQIIR_HP30HZ20dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xe0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_16khz.m4 index 5242fc4bc9e9..e0fb34a92288 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_16khz.m4 @@ -1,5 +1,5 @@ # 40 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP40HZ0dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_48khz.m4 index ea28ad008dcd..a333f16e81db 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_40hz_0db_48khz.m4 @@ -1,5 +1,5 @@ # 40 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP40HZ0dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_16khz.m4 index ca5505f84b2f..45c554148392 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_16khz.m4 @@ -1,5 +1,5 @@ # 40 Hz second order high-pass, gain 20 dB, created with example_iir_eq.m 30-Mar-2020 -CONTROLBYTES_PRIV(EQIIR_HP40HZ20dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xe0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_48khz.m4 index 7862a0e9e5ba..bdc8d97bcd17 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_40hz_20db_48khz.m4 @@ -1,5 +1,5 @@ # 40 Hz second order high-pass, gain 20 dB, created with example_iir_eq.m 30-Mar-2020 -CONTROLBYTES_PRIV(EQIIR_HP40HZ20dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xe0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_16khz.m4 index 4d59264b2337..fecc8d5fc7ab 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_16khz.m4 @@ -1,5 +1,5 @@ # 50 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP50HZ0dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_48khz.m4 index 11457d497d62..031a9b7fa352 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_50hz_0db_48khz.m4 @@ -1,5 +1,5 @@ # 50 Hz second order high-pass, gain 0 dB, created with example_iir_eq.m 27-Nov-2019 -CONTROLBYTES_PRIV(EQIIR_HP50HZ0dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0xc0,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_16khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_16khz.m4 index 40aba6f8ba4d..4c7df7301c88 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_16khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_16khz.m4 @@ -1,5 +1,5 @@ # 50 Hz second order high-pass and +20 dB gain 13-Aug-2019 -CONTROLBYTES_PRIV(EQIIR_HP50HZ20dB16K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0x00,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_48khz.m4 b/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_48khz.m4 index d22924ef5a55..3aced8f0a592 100644 --- a/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_48khz.m4 +++ b/tools/topology/m4/eq_iir_coef_highpass_50hz_20db_48khz.m4 @@ -1,5 +1,5 @@ # 50 Hz second order high-pass and +20 dB gain 18-Dec-2018 -CONTROLBYTES_PRIV(EQIIR_HP50HZ20dB48K_priv, +CONTROLBYTES_PRIV(DEF_EQIIR_PRIV, ` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' ` 0x58,0x00,0x00,0x00,0x00,0x00,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' diff --git a/tools/topology/sof-cml-rt5682.m4 b/tools/topology/sof-cml-rt5682.m4 index cbab2009b68f..44d1aff88dfa 100644 --- a/tools/topology/sof-cml-rt5682.m4 +++ b/tools/topology/sof-cml-rt5682.m4 @@ -19,15 +19,22 @@ include(`platform/intel/'PLATFORM`.m4') DEBUG_START +# if XPROC is not defined, define with default pipe +ifdef(`HSMICPROC', , `define(HSMICPROC, volume)') +ifdef(`HSEARPROC', , `define(HSEARPROC, volume)') +ifdef(`DMICPROC', , `define(DMICPROC, passthrough)') +ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, volume)') + # # Define the pipelines # -# PCM0 <---> volume <----> SSP(SSP_INDEX, BE link 0) -# PCM1 <------------------ DMIC01 (dmic0 capture, , BE link 1) +`# PCM0 ---> 'HSEARPROC` ----> SSP(SSP_INDEX, BE link 0)' +`# PCM0 <--- 'HSMICPROC` <---- SSP(SSP_INDEX, BE link 0)' +`# PCM1 <--- 'DMICPROC` <----- DMIC01 (dmic0 capture, , BE link 1)' # PCM2 ----> volume -----> iDisp1 (HDMI/DP playback, BE link 3) # PCM3 ----> volume -----> iDisp2 (HDMI/DP playback, BE link 4) # PCM4 ----> volume -----> iDisp3 (HDMI/DP playback, BE link 5) -# PCM8 <---- volume <----- DMIC16k (dmic16k, BE link 2) +`# PCM8 <---- 'DMIC16KPROC` <----- DMIC16k (dmic16k, BE link 2)' # dnl PIPELINE_PCM_ADD(pipeline, @@ -38,21 +45,21 @@ dnl time_domain, sched_comp) # Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s24le. # 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, +PIPELINE_PCM_ADD(sof/pipe-`HSEARPROC'-playback.m4, 1, 0, 2, s24le, 1000, 0, 0, 48000, 48000, 48000) # Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s24le. # 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-`HSMICPROC'-capture.m4, 2, 0, 2, s24le, 1000, 0, 0, 48000, 48000, 48000) # Passthrough capture pipeline 3 on PCM 1 using max 4 channels. # 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-`DMICPROC'-capture.m4, 3, 1, 4, s32le, 1000, 0, 0, 48000, 48000, 48000) @@ -80,7 +87,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, # Passthrough capture pipeline 7 on PCM 5 using max 2 channels. # Schedule 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture-16khz.m4, +PIPELINE_PCM_ADD(sof/pipe-`DMIC16KPROC'-capture-16khz.m4, 8, 8, 2, s24le, 1000, 0, 0, 16000, 16000, 16000) diff --git a/tools/topology/sof/pipe-eq-fir-capture.m4 b/tools/topology/sof/pipe-eq-fir-capture.m4 index 65e592c1df4f..8cbe1e881b40 100644 --- a/tools/topology/sof/pipe-eq-fir-capture.m4 +++ b/tools/topology/sof/pipe-eq-fir-capture.m4 @@ -17,8 +17,12 @@ include(`eq_fir.m4') # Controls # -# Use flat response -include(`eq_fir_coef_flat.m4') +define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) +define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) + +# define filter. eq_fir_coef_flat.m4 is set by default +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 define(MY_CONTROLBYTES, concat(`EQFIR_CONTROLBYTES_', PIPELINE_ID)) @@ -32,7 +36,7 @@ C_CONTROLBYTES(MY_CONTROLBYTES, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 4096), , - EQFIR_priv) + DEF_EQFIR_PRIV) # # Components and Buffers @@ -80,3 +84,5 @@ PCM_CAPABILITIES(EQ FIR Capture PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, 2, 16, 192, 16384, 65536, 65536) undefine(`MY_CONTROLBYTES') +undefine(`MY_EQFIR_COEF') +undefine(`MY_EQFIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-fir-playback.m4 b/tools/topology/sof/pipe-eq-fir-playback.m4 index 906ca3cd05e3..d8bc8aae03b2 100644 --- a/tools/topology/sof/pipe-eq-fir-playback.m4 +++ b/tools/topology/sof/pipe-eq-fir-playback.m4 @@ -17,8 +17,12 @@ include(`eq_fir.m4') # Controls # -# Use coefficients for flat frequency response -include(`eq_fir_coef_flat.m4') +define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) +define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) + +# define filter. eq_fir_coef_flat.m4 is set by default +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 define(MY_CONTROLBYTES, concat(`EQFIR_CONTROLBYTES_', PIPELINE_ID)) @@ -30,7 +34,7 @@ C_CONTROLBYTES(MY_CONTROLBYTES, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 4096), , - EQFIR_priv) + DEF_EQFIR_PRIV) # # Components and Buffers @@ -80,3 +84,5 @@ PCM_CAPABILITIES(EQ FIR Playback PCM_ID, `S32_LE,S24_LE,S16_LE', 2, 16, 192, 16384, 65536, 65536) undefine(`MY_CONTROLBYTES') +undefine(`MY_EQFIR_COEF') +undefine(`MY_EQFIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-fir-volume-capture.m4 b/tools/topology/sof/pipe-eq-fir-volume-capture.m4 new file mode 100644 index 000000000000..ae30bbea3fad --- /dev/null +++ b/tools/topology/sof/pipe-eq-fir-volume-capture.m4 @@ -0,0 +1,129 @@ +# Passthrough with volume Pipeline and PCM +# +# Pipeline Endpoints for connection are :- +# +# host PCM_C <-- B0 <-- Volume 0 <-- B1 <-- EQ-FIR <-- B2 <-- source DAI0 + +# Include topology builder +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`pga.m4') +include(`dai.m4') +include(`mixercontrol.m4') +include(`pipeline.m4') +include(`bytecontrol.m4') +include(`eq_fir.m4') + +# +# Controls +# +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, + 256 binds the mixer control to volume get/put handlers, + 256, 256), + CONTROLMIXER_MAX(, 80), + false, + CONTROLMIXER_TLV(TLV 80 steps from -50dB to +30dB for 1dB, vtlv_m50s1), + Channel register and shift for Front Left/Right, + LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) + +# +# Volume Configuration +# + +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) + +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, +LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' + ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"')) + +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) + +# +# FIR EQ +# + +define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) +define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) + +# define filter. eq_fir_coef_flat.m4 is set by default +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +include(PIPELINE_FILTER2) + +# EQ Bytes control with max value of 255 +C_CONTROLBYTES(DEF_EQFIR_COEF, PIPELINE_ID, + CONTROLBYTES_OPS(bytes, + 258 binds the mixer control to bytes get/put handlers, + 258, 258), + CONTROLBYTES_EXTOPS( + 258 binds the mixer control to bytes get/put handlers, + 258, 258), + , , , + CONTROLBYTES_MAX(, 4096), + , + DEF_EQFIR_PRIV) + +# +# Components and Buffers +# + +# Host "Passthrough Capture" PCM +# with 0 sink and 2 source periods +W_PCM_CAPTURE(PCM_ID, Passthrough Capture, 0, 2) + +# "Volume" has 2 sink and 2 source periods +W_PGA(0, PIPELINE_FORMAT, 2, 2, DEF_PGA_CONF, + LIST(` ', "PIPELINE_ID Master Capture Volume")) + +# "EQ 0" has 2 sink period and x source periods +W_EQ_FIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, + LIST(` ', "DEF_EQFIR_COEF")) + +# Capture Buffers +W_BUFFER(0, COMP_BUFFER_SIZE(2, + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, + COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), + PLATFORM_HOST_MEM_CAP) +W_BUFFER(1, COMP_BUFFER_SIZE(2, + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, + COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), + PLATFORM_HOST_MEM_CAP) +W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS, + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, + COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), + PLATFORM_DAI_MEM_CAP) + +# +# Pipeline Graph +# +# host PCM_C <-- B0 <-- Volume 0 <-- B1 <-- EQ-FIR 0 <-- B2 <-- sink DAI0 + +P_GRAPH(pipe-pass-vol-capture-PIPELINE_ID, PIPELINE_ID, + LIST(` ', + `dapm(N_PCMC(PCM_ID), N_BUFFER(0))', + `dapm(N_BUFFER(0), N_PGA(0))', + `dapm(N_PGA(0), N_BUFFER(1))', + `dapm(N_BUFFER(1), N_EQ_FIR(0))', + `dapm(N_EQ_FIR(0), N_BUFFER(2))')) + +# +# Pipeline Source and Sinks +# +indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(2)) +indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Capture PCM_ID) + +# +# PCM Configuration +# + +PCM_CAPABILITIES(Passthrough Capture PCM_ID, `S32_LE,S24_LE,S16_LE', + PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS, + 2, 16, 192, 16384, 65536, 65536) + +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQFIR_COEF') +undefine(`DEF_EQFIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-fir-volume-playback.m4 b/tools/topology/sof/pipe-eq-fir-volume-playback.m4 index b85e0c3ce30d..c4bfd2abf103 100644 --- a/tools/topology/sof/pipe-eq-fir-volume-playback.m4 +++ b/tools/topology/sof/pipe-eq-fir-volume-playback.m4 @@ -31,14 +31,21 @@ C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID, # Volume configuration # -W_VENDORTUPLES(playback_pga_tokens, sof_volume_tokens, +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) + +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"')) -W_DATA(playback_pga_conf, playback_pga_tokens) +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) + +define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) +define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) # EQ initial parameters, in this case flat response -include(`eq_fir_coef_flat.m4') +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 C_CONTROLBYTES(EQFIR, PIPELINE_ID, @@ -47,7 +54,7 @@ C_CONTROLBYTES(EQFIR, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 304), , - EQFIR_priv) + DEF_EQFIR_PRIV) # # Components and Buffers @@ -58,10 +65,10 @@ C_CONTROLBYTES(EQFIR, PIPELINE_ID, W_PCM_PLAYBACK(PCM_ID, Passthrough Playback, 2, 0) # "Volume" has 2 source and x sink periods -W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID Master Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF, LIST(` ', "PIPELINE_ID Master Playback Volume")) # "EQ 0" has 2 sink period and 2 source periods -W_EQ_FIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "EQFIR")) +W_EQ_FIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "DEF_EQFIR_COEF")) # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -100,3 +107,7 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Playback PCM_I # PCM_CAPABILITIES(Passthrough Playback PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQFIR_COEF') +undefine(`DEF_EQFIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-iir-capture.m4 b/tools/topology/sof/pipe-eq-iir-capture.m4 index 6fa515829647..0ce04f71214f 100644 --- a/tools/topology/sof/pipe-eq-iir-capture.m4 +++ b/tools/topology/sof/pipe-eq-iir-capture.m4 @@ -17,12 +17,16 @@ include(`eq_iir.m4') # Controls # -# Use 40 Hz highpass response with 0 dB gain -include(`eq_iir_coef_highpass_40hz_0db_48khz.m4') +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) + +# By default, use 40 Hz highpass response with 0 dB gain +# TODO: need to implement middle level macro handler per pipeline +ifdef(`DMICPROC_FILTER1', , `define(DMICPROC_FILTER1, eq_iir_coef_highpass_40hz_0db_48khz.m4)') +include(DMICPROC_FILTER1) # EQ Bytes control with max value of 255 -define(MY_CONTROLBYTES, concat(`EQIIR_CONTROLBYTES_', PIPELINE_ID)) -C_CONTROLBYTES(MY_CONTROLBYTES, PIPELINE_ID, +C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), @@ -32,7 +36,7 @@ C_CONTROLBYTES(MY_CONTROLBYTES, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 1024), , - EQIIR_HP40HZ0dB48K_priv) + DEF_EQIIR_PRIV) # # Components and Buffers @@ -43,7 +47,7 @@ C_CONTROLBYTES(MY_CONTROLBYTES, PIPELINE_ID, W_PCM_CAPTURE(PCM_ID, EQ IIR Capture, 0, 2) # "EQ 0" has 2 sink period and x source periods -W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "MY_CONTROLBYTES")) +W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "DEF_EQIIR_COEF")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -79,4 +83,5 @@ PCM_CAPABILITIES(EQ IIR Capture PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) -undefine(`MY_CONTROLBYTES') +undefine(`DEF_EQIIR_COEF') +undefine(`DEF_EQIIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-iir-playback.m4 b/tools/topology/sof/pipe-eq-iir-playback.m4 index 4ee35bc5f1cb..992a0931beda 100644 --- a/tools/topology/sof/pipe-eq-iir-playback.m4 +++ b/tools/topology/sof/pipe-eq-iir-playback.m4 @@ -17,8 +17,12 @@ include(`eq_iir.m4') # Controls # -# Use coefficients for flat frequency response -include(`eq_iir_coef_flat.m4') +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) + +# define filter. eq_iir_coef_flat.m4 is set by default +ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_flat.m4)') +include(PIPELINE_FILTER1) # EQ Bytes control with max value of 255 define(MY_CONTROLBYTES, concat(`EQIIR_CONTROLBYTES_', PIPELINE_ID)) @@ -30,7 +34,7 @@ C_CONTROLBYTES(MY_CONTROLBYTES, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 1024), , - EQIIR_priv) + DEF_EQIIR_PRIV) # # Components and Buffers @@ -80,3 +84,5 @@ PCM_CAPABILITIES(EQ IIR Playback PCM_ID, `S32_LE,S24_LE,S16_LE', 2, 16, 192, 16384, 65536, 65536) undefine(`MY_CONTROLBYTES') +undefine(`DEF_EQIIR_COEF') +undefine(`DEF_EQIIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-iir-volume-playback.m4 b/tools/topology/sof/pipe-eq-iir-volume-playback.m4 index f433a4bf5dde..883d21f3bd37 100644 --- a/tools/topology/sof/pipe-eq-iir-volume-playback.m4 +++ b/tools/topology/sof/pipe-eq-iir-volume-playback.m4 @@ -31,23 +31,33 @@ C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID, # Volume configuration # -W_VENDORTUPLES(playback_pga_tokens, sof_volume_tokens, +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) + +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"')) -W_DATA(playback_pga_conf, playback_pga_tokens) +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) + +# +# IIR EQ +# +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) -# EQ initial parameters, in this case flat response -include(`eq_iir_coef_flat.m4') +# define filter. eq_iir_coef_flat.m4 is set by default +ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_flat.m4)') +include(PIPELINE_FILTER1) # EQ Bytes control with max value of 255 -C_CONTROLBYTES(EQIIR, PIPELINE_ID, +C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258), , , , CONTROLBYTES_MAX(, 304), , - EQIIR_priv) + DEF_EQIIR_PRIV) # # Components and Buffers @@ -58,10 +68,10 @@ C_CONTROLBYTES(EQIIR, PIPELINE_ID, W_PCM_PLAYBACK(PCM_ID, Passthrough Playback, 2, 0) # "Volume" has 2 source and x sink periods -W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID Master Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF, LIST(` ', "PIPELINE_ID Master Playback Volume")) # "EQ 0" has 2 sink period and 2 source periods -W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "EQIIR")) +W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "DEF_EQIIR_COEF")) # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -100,3 +110,7 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Playback PCM_I # PCM_CAPABILITIES(Passthrough Playback PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQIIR_COEF') +undefine(`DEF_EQIIR_PRIV') diff --git a/tools/topology/sof/pipe-highpass-capture.m4 b/tools/topology/sof/pipe-highpass-capture.m4 index ecc2a8495911..ec928ce46a49 100644 --- a/tools/topology/sof/pipe-highpass-capture.m4 +++ b/tools/topology/sof/pipe-highpass-capture.m4 @@ -33,23 +33,28 @@ C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, # Volume Configuration # -define(MY_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) -define(MY_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) -W_VENDORTUPLES(MY_PGA_TOKENS, sof_volume_tokens, +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "400"')) -W_DATA(MY_PGA_CONF, MY_PGA_TOKENS) +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) # # IIR configuration # -include(`eq_iir_coef_highpass_40hz_0db_48khz.m4') +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) + +# By default, use 40 Hz highpass response with 0 dB gain +ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_highpass_40hz_0db_48khz.m4)') +include(PIPELINE_FILTER1) # EQ Bytes control with max value of 255 -define(MY_EQIIR_BYTES, concat(`eqiir_bytes_', PIPELINE_ID)) -C_CONTROLBYTES(MY_EQIIR_BYTES, PIPELINE_ID, +define(DEF_EQIIR_COEF, concat(`eqiir_bytes_', PIPELINE_ID)) +C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), @@ -59,7 +64,7 @@ C_CONTROLBYTES(MY_EQIIR_BYTES, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 304), , - EQIIR_HP40HZ0dB48K_priv) + DEF_EQIIR_PRIV) # # Components and Buffers @@ -70,12 +75,12 @@ C_CONTROLBYTES(MY_EQIIR_BYTES, PIPELINE_ID, W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2) # "Volume" has 2 sink and 2 source periods -W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, MY_PGA_CONF, +W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, DEF_PGA_CONF, LIST(` ', "PIPELINE_ID Master Capture Volume")) # "EQ_IIR 0" has 2 sink and x source periods W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, - LIST(` ', "MY_EQIIR_BYTES")) + LIST(` ', "DEF_EQIIR_COEF")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -118,6 +123,7 @@ PCM_CAPABILITIES(Highpass Capture PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) -undefine(`MY_PGA_TOKENS') -undefine(`MY_PGA_CONF') -undefine(`MY_EQIIR_BYTES') +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQFIR_COEF') +undefine(`DEF_EQFIR_PRIV') diff --git a/tools/topology/sof/pipe-highpass-switch-capture.m4 b/tools/topology/sof/pipe-highpass-switch-capture.m4 index 8377c8a4520b..cc1a1a7f5492 100644 --- a/tools/topology/sof/pipe-highpass-switch-capture.m4 +++ b/tools/topology/sof/pipe-highpass-switch-capture.m4 @@ -43,23 +43,27 @@ C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID, # Volume Configuration # -define(MY_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) -define(MY_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) -W_VENDORTUPLES(MY_PGA_TOKENS, sof_volume_tokens, +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "400"')) -W_DATA(MY_PGA_CONF, MY_PGA_TOKENS) +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) # # IIR configuration # -include(`eq_iir_coef_highpass_40hz_0db_48khz.m4') +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) + +# By default, use 40 Hz highpass response with 0 dB gain +ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_highpass_40hz_0db_48khz.m4)') +include(PIPELINE_FILTER1) # EQ Bytes control with max value of 255 -define(MY_EQIIR_BYTES, concat(`eqiir_bytes_', PIPELINE_ID)) -C_CONTROLBYTES(MY_EQIIR_BYTES, PIPELINE_ID, +C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), @@ -69,7 +73,7 @@ C_CONTROLBYTES(MY_EQIIR_BYTES, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 304), , - EQIIR_HP40HZ0dB48K_priv) + DEF_EQIIR_PRIV) # # Components and Buffers @@ -80,13 +84,13 @@ C_CONTROLBYTES(MY_EQIIR_BYTES, PIPELINE_ID, W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2) # "Volume" has 2 sink and 2 source periods -W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, MY_PGA_CONF, +W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, DEF_PGA_CONF, LIST(` ', "PIPELINE_ID Master Capture Volume", "PIPELINE_ID Master Capture Switch")) # "EQ_IIR 0" has 2 sink and x source periods W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, - LIST(` ', "MY_EQIIR_BYTES")) + LIST(` ', "DEF_EQIIR_COEF")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -129,6 +133,7 @@ PCM_CAPABILITIES(Highpass Capture PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) -undefine(`MY_PGA_TOKENS') -undefine(`MY_PGA_CONF') -undefine(`MY_EQIIR_BYTES') +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQIIR_COEF') +undefine(`DEF_EQIIR_PRIV') From da9050bb8a2ee6a85f01403714c0df2c0e0e4266 Mon Sep 17 00:00:00 2001 From: Fred Oh Date: Thu, 2 Apr 2020 18:41:39 -0700 Subject: [PATCH 2/2] topology: set DMIC pipe with eq-iir with 40 Hz highpass For headset playback or capture, default pipe is volume. If The high pass filter is required to prevent HDA codec headset glitches, it can be set by HSMICPROC=eq-iir-volume. It use use 40 Hz high pass filter with +0 db boost. If there is DMIC, this set default pipe as eq-iir, which use the same 40 Hz high-pass filter too. For DMIC16K, 40 Hz high-pass for 16khz version filter is used. Default coefficient for FIR/IIR is changed fr m coef flat to coef pass. Pass configuration has the advantage of low system load. eq_fir_coef_flat.m4 to eq_fir_coef_pass.m4 eq_iir_coef_flat.m4 to eq_iir_coef_pass.m4 Below pipe files are renamed for naming convention, pipe-eq-volume-playback.m4 -> pipe-eq-iir-eq-fir-volume-playback.m4 pipe-eq-capture-16khz.m4 -> pipe-eq-iir-volume-capture-16khz.m4 pipe-eq-capture.m4 -> pipe-eq-iir-volume-capture.m4 Signed-off-by: Fred Oh --- tools/topology/CMakeLists.txt | 14 ++--- .../platform/intel/intel-generic-dmic.m4 | 4 +- tools/topology/sof-apl-pcm512x.m4 | 4 +- tools/topology/sof-cml-rt5682.m4 | 4 +- tools/topology/sof/pipe-eq-fir-capture.m4 | 6 +-- tools/topology/sof/pipe-eq-fir-playback.m4 | 4 +- .../sof/pipe-eq-fir-volume-capture.m4 | 4 +- .../sof/pipe-eq-fir-volume-playback.m4 | 4 +- tools/topology/sof/pipe-eq-iir-capture.m4 | 2 +- ... => pipe-eq-iir-eq-fir-volume-playback.m4} | 53 ++++++++++++++----- ...m4 => pipe-eq-iir-volume-capture-16khz.m4} | 29 +++++++--- ...pture.m4 => pipe-eq-iir-volume-capture.m4} | 40 +++++++++----- 12 files changed, 111 insertions(+), 57 deletions(-) rename tools/topology/sof/{pipe-eq-volume-playback.m4 => pipe-eq-iir-eq-fir-volume-playback.m4} (69%) rename tools/topology/sof/{pipe-eq-capture-16khz.m4 => pipe-eq-iir-volume-capture-16khz.m4} (76%) rename tools/topology/sof/{pipe-eq-capture.m4 => pipe-eq-iir-volume-capture.m4} (73%) diff --git a/tools/topology/CMakeLists.txt b/tools/topology/CMakeLists.txt index 73e2d1859dad..91ce7e7dc733 100644 --- a/tools/topology/CMakeLists.txt +++ b/tools/topology/CMakeLists.txt @@ -26,8 +26,8 @@ set(TPLGS "sof-hda-generic\;sof-hda-generic\;-DCHANNELS=0\;-DPPROC=volume" "sof-hda-generic\;sof-hda-generic-2ch\;-DCHANNELS=2\;-DPPROC=volume" "sof-hda-generic\;sof-hda-generic-4ch\;-DCHANNELS=4\;-DPPROC=volume" - "sof-hda-generic\;sof-hda-generic-eq-2ch\;-DCHANNELS=2\;-DPPROC=eq-volume" - "sof-hda-generic\;sof-hda-generic-eq-4ch\;-DCHANNELS=4\;-DPPROC=eq-volume" + "sof-hda-generic\;sof-hda-generic-eq-2ch\;-DCHANNELS=2\;-DPPROC=eq-iir-eq-fir-volume" + "sof-hda-generic\;sof-hda-generic-eq-4ch\;-DCHANNELS=4\;-DPPROC=eq-iir-eq-fir-volume" "sof-hda-generic-kwd\;sof-hda-generic-2ch-kwd\;-DCHANNELS=2" "sof-hda-generic-kwd\;sof-hda-generic-4ch-kwd\;-DCHANNELS=4" "sof-hda-generic-idisp\;sof-hda-generic-idisp\;-DCHANNELS=0" @@ -72,11 +72,11 @@ set(TPLGS "sof-apl-da7219\;sof-apl-da7219" "sof-glk-da7219-kwd\;sof-glk-da7219-kwd" "sof-glk-da7219\;sof-glk-da7219" - "sof-glk-da7219\;sof-glk-eq-da7219\;-DDMICPROC=eq" + "sof-glk-da7219\;sof-glk-eq-da7219\;-DDMICPROC=eq-iir-volume" "sof-glk-rt5682\;sof-glk-rt5682" "sof-icl-nocodec\;sof-icl-nocodec" - "sof-apl-pcm512x-nohdmi\;sof-apl-eq-pcm512x\;-DPPROC=eq-volume" - "sof-apl-dmic\;sof-apl-eq-dmic\;-DCHANNELS=4\;-DCPROC=eq" + "sof-apl-pcm512x-nohdmi\;sof-apl-eq-pcm512x\;-DPPROC=eq-iir-eq-fir-volume" + "sof-apl-dmic\;sof-apl-eq-dmic\;-DCHANNELS=4\;-DCPROC=eq-iir-volume" "sof-apl-src-dmic\;sof-apl-src-dmic" "sof-apl-dmic-a2ch\;sof-apl-dmic-a2ch" "sof-apl-dmic-b2ch\;sof-apl-dmic-b2ch" @@ -99,7 +99,7 @@ set(TPLGS "sof-apl-src-pcm512x\;sof-apl-src-pcm512x" "sof-cml-rt5682\;sof-cml-rt5682\;-DPLATFORM=cml" "sof-cml-rt5682\;sof-cml-eq-fir-rt5682\;-DPLATFORM=cml\;-DHSMICPROC=eq-fir-volume" - "sof-cml-rt5682\;sof-cml-eq-fir-loud-rt5682\;-DPLATFORM=cml\;-DHSMICPROC=eq-fir-volume\;-DPIPELINE_FILTER1=eq_fir_coef_loudness.m4" + "sof-cml-rt5682\;sof-cml-eq-fir-loud-rt5682\;-DPLATFORM=cml\;-DHSEARPROC=eq-iir-volume\;-DPIPELINE_FILTER1=eq_iir_coef_loudness.m4\;-DHSMICPROC=eq-fir-volume\;-DPIPELINE_FILTER2=eq_fir_coef_loudness.m4" "sof-cml-rt5682\;sof-cml-eq-iir-rt5682\;-DPLATFORM=cml\;-DHSEARPROC=eq-iir-volume" "sof-cml-rt5682\;sof-whl-rt5682\;-DPLATFORM=whl" "sof-cml-rt5682\;sof-icl-rt5682\;-DPLATFORM=icl" @@ -113,7 +113,7 @@ set(TPLGS "sof-cml-rt5682-max98357a\;sof-cml-rt5682-max98357a\;-DPLATFORM=cml" "sof-cml-demux-rt5682-max98357a\;sof-cml-demux-rt5682-max98357a\;-DPLATFORM=cml" "sof-cml-rt1011-rt5682\;sof-cml-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=volume" - "sof-cml-rt1011-rt5682\;sof-cml-eq-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=eq-volume" + "sof-cml-rt1011-rt5682\;sof-cml-eq-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=eq-iir-eq-fir-volume" "sof-tgl-nocodec\;sof-tgl-nocodec" "sof-tgl-rt711-i2s-rt1308\;sof-tgl-rt711-i2s-rt1308\;-DHDMI=1" "sof-tgl-rt711-i2s-rt1308\;sof-tgl-rt711-i2s-rt1308-nohdmi" diff --git a/tools/topology/platform/intel/intel-generic-dmic.m4 b/tools/topology/platform/intel/intel-generic-dmic.m4 index 0e8daf7dc268..2be95f5e1cfc 100644 --- a/tools/topology/platform/intel/intel-generic-dmic.m4 +++ b/tools/topology/platform/intel/intel-generic-dmic.m4 @@ -21,14 +21,14 @@ dnl time_domain, sched_comp) # Passthrough capture pipeline using max channels defined by CHANNELS. # Set 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-eq-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture.m4, DMIC_PIPELINE_48k_ID, DMIC_DAI_LINK_48k_ID, CHANNELS, s32le, 1000, 0, 0, 48000, 48000, 48000) # Passthrough capture pipeline using max channels defined by CHANNELS. # Schedule with 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-eq-capture-16khz.m4, +PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture-16khz.m4, DMIC_PIPELINE_16k_ID, DMIC_DAI_LINK_16k_ID, CHANNELS, s32le, 1000, 0, 0, 16000, 16000, 16000) diff --git a/tools/topology/sof-apl-pcm512x.m4 b/tools/topology/sof-apl-pcm512x.m4 index 45bda529c3f1..a9b63b3ca15d 100644 --- a/tools/topology/sof-apl-pcm512x.m4 +++ b/tools/topology/sof-apl-pcm512x.m4 @@ -75,14 +75,14 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, # DMIC passthrough capture pipeline 7 on PCM 4 using max 2 channels. # 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-eq-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture.m4, 7, 5, 4, s32le, 1000, 0, 0, 48000, 48000, 48000) # DMIC16kHz passthrough capture pipeline 8 on PCM 5 using max 2 channels. # 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-eq-capture-16khz.m4, +PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture-16khz.m4, 8, 6, 2, s16le, 1000, 0, 0, 16000, 16000, 16000) diff --git a/tools/topology/sof-cml-rt5682.m4 b/tools/topology/sof-cml-rt5682.m4 index 44d1aff88dfa..1c8432d12fde 100644 --- a/tools/topology/sof-cml-rt5682.m4 +++ b/tools/topology/sof-cml-rt5682.m4 @@ -22,8 +22,8 @@ DEBUG_START # if XPROC is not defined, define with default pipe ifdef(`HSMICPROC', , `define(HSMICPROC, volume)') ifdef(`HSEARPROC', , `define(HSEARPROC, volume)') -ifdef(`DMICPROC', , `define(DMICPROC, passthrough)') -ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, volume)') +ifdef(`DMICPROC', , `define(DMICPROC, eq-iir-volume)') +ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, eq-iir-volume)') # # Define the pipelines diff --git a/tools/topology/sof/pipe-eq-fir-capture.m4 b/tools/topology/sof/pipe-eq-fir-capture.m4 index 8cbe1e881b40..6a608b173725 100644 --- a/tools/topology/sof/pipe-eq-fir-capture.m4 +++ b/tools/topology/sof/pipe-eq-fir-capture.m4 @@ -20,8 +20,8 @@ include(`eq_fir.m4') define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) -# define filter. eq_fir_coef_flat.m4 is set by default -ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +# define filter. eq_fir_coef_pass.m4 is set by default +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)') include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 @@ -54,7 +54,7 @@ W_BUFFER(0, COMP_BUFFER_SIZE(2, COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP) -W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS, +W_BUFFER(1, COMP_BUFFER_SIZE(DAI_PERIODS, COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP) diff --git a/tools/topology/sof/pipe-eq-fir-playback.m4 b/tools/topology/sof/pipe-eq-fir-playback.m4 index d8bc8aae03b2..a078a12d1aa1 100644 --- a/tools/topology/sof/pipe-eq-fir-playback.m4 +++ b/tools/topology/sof/pipe-eq-fir-playback.m4 @@ -20,8 +20,8 @@ include(`eq_fir.m4') define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) -# define filter. eq_fir_coef_flat.m4 is set by default -ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +# define filter. eq_fir_coef_pass.m4 is set by default +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)') include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 diff --git a/tools/topology/sof/pipe-eq-fir-volume-capture.m4 b/tools/topology/sof/pipe-eq-fir-volume-capture.m4 index ae30bbea3fad..91d47caca550 100644 --- a/tools/topology/sof/pipe-eq-fir-volume-capture.m4 +++ b/tools/topology/sof/pipe-eq-fir-volume-capture.m4 @@ -49,8 +49,8 @@ W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) -# define filter. eq_fir_coef_flat.m4 is set by default -ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +# define filter. eq_fir_coef_pass.m4 is set by default +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)') include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 diff --git a/tools/topology/sof/pipe-eq-fir-volume-playback.m4 b/tools/topology/sof/pipe-eq-fir-volume-playback.m4 index c4bfd2abf103..bbe3dddf26d2 100644 --- a/tools/topology/sof/pipe-eq-fir-volume-playback.m4 +++ b/tools/topology/sof/pipe-eq-fir-volume-playback.m4 @@ -43,8 +43,8 @@ W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) -# EQ initial parameters, in this case flat response -ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)') +# define filter. eq_fir_coef_pass.m4 is set by default +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)') include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 diff --git a/tools/topology/sof/pipe-eq-iir-capture.m4 b/tools/topology/sof/pipe-eq-iir-capture.m4 index 0ce04f71214f..55241a235cac 100644 --- a/tools/topology/sof/pipe-eq-iir-capture.m4 +++ b/tools/topology/sof/pipe-eq-iir-capture.m4 @@ -54,7 +54,7 @@ W_BUFFER(0, COMP_BUFFER_SIZE(2, COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP) -W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS, +W_BUFFER(1, COMP_BUFFER_SIZE(DAI_PERIODS, COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP) diff --git a/tools/topology/sof/pipe-eq-volume-playback.m4 b/tools/topology/sof/pipe-eq-iir-eq-fir-volume-playback.m4 similarity index 69% rename from tools/topology/sof/pipe-eq-volume-playback.m4 rename to tools/topology/sof/pipe-eq-iir-eq-fir-volume-playback.m4 index 930c30efc316..9b5cb9debae4 100644 --- a/tools/topology/sof/pipe-eq-volume-playback.m4 +++ b/tools/topology/sof/pipe-eq-iir-eq-fir-volume-playback.m4 @@ -33,35 +33,54 @@ C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID, # Volume configuration # -W_VENDORTUPLES(playback_pga_tokens, sof_volume_tokens, +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) + +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"')) -W_DATA(playback_pga_conf, playback_pga_tokens) +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) + +# +# IIR EQ +# + +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) -# Use coefficients for flat frequency response -include(`eq_iir_coef_flat.m4') +# By default, use coefficients for pass frequency response +ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_pass.m4)') +include(PIPELINE_FILTER1) # EQ Bytes control with max value of 255 -C_CONTROLBYTES(EQIIR, PIPELINE_ID, +C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258), , , , CONTROLBYTES_MAX(, 304), , - EQIIR_priv) + DEF_EQIIR_PRIV) -# Use coefficients for flat frequency response -include(`eq_fir_coef_flat.m4') +# +# FIR EQ +# + +define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID)) +define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID)) + +# By default, use coefficients for pass frequency response +ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)') +include(PIPELINE_FILTER2) # EQ Bytes control with max value of 255 -C_CONTROLBYTES(EQFIR, PIPELINE_ID, +C_CONTROLBYTES(DEF_EQFIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258), , , , CONTROLBYTES_MAX(, 4096), , - EQFIR_priv) + DEF_EQFIR_PRIV) # # Components and Buffers @@ -72,13 +91,17 @@ C_CONTROLBYTES(EQFIR, PIPELINE_ID, W_PCM_PLAYBACK(PCM_ID, Passthrough Playback, 2, 0) # "Volume" has 2 source and x sink periods -W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID Master Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF, LIST(` ', "PIPELINE_ID Master Playback Volume")) # "EQ 0" has 2 sink period and 2 source periods -W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "EQIIR")) +W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "DEF_EQIIR_COEF")) # "EQ 0" has 2 sink period and 2 source periods -W_EQ_FIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "EQFIR")) +W_EQ_FIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "DEF_EQFIR_COEF")) + +# "Volume" has x sink and 2 source periods +W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF, + LIST(` ', "PIPELINE_ID Master Playback Volume")) # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -121,3 +144,7 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Playback PCM_I # PCM_CAPABILITIES(Passthrough Playback PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQIIR_COEF') +undefine(`DEF_EQIIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-capture-16khz.m4 b/tools/topology/sof/pipe-eq-iir-volume-capture-16khz.m4 similarity index 76% rename from tools/topology/sof/pipe-eq-capture-16khz.m4 rename to tools/topology/sof/pipe-eq-iir-volume-capture-16khz.m4 index ac9b0e7d490c..fed20fe99348 100644 --- a/tools/topology/sof/pipe-eq-capture-16khz.m4 +++ b/tools/topology/sof/pipe-eq-iir-volume-capture-16khz.m4 @@ -33,17 +33,25 @@ C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) # Volume Configuration -W_VENDORTUPLES(capture_pga_tokens, sof_volume_tokens, +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) + +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"')) -W_DATA(capture_pga_conf, capture_pga_tokens) +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) + +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) -# Use 50 Hz highpass response with +20 dB gain -include(`eq_iir_coef_highpass_50hz_20db_16khz.m4') +# By default, use 40 Hz highpass response with +0 dB gain for 16khz +# TODO: need to implement middle level macro handler per pipeline +ifdef(`DMIC16KPROC_FILTER1', , `define(DMIC16KPROC_FILTER1, eq_iir_coef_highpass_40hz_0db_16khz.m4)') +include(DMIC16KPROC_FILTER1) # EQ Bytes control with max value of 255 -C_CONTROLBYTES(EQIIR_C16, PIPELINE_ID, +C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), @@ -53,7 +61,7 @@ C_CONTROLBYTES(EQIIR_C16, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 304), , - EQIIR_HP50HZ20dB16K_priv) + DEF_EQIIR_PRIV) # # Components and Buffers @@ -65,11 +73,11 @@ W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2) # "Volume" has 2 source and 2 sink periods W_PGA(0, PIPELINE_FORMAT, 2, 2, - capture_pga_conf, LIST(` ', + DEF_PGA_CONF, LIST(` ', "CONTROL_NAME")) # "EQ 0" has 2 sink period and x source periods -W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "EQIIR_C16")) +W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "DEF_EQIIR_COEF")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -112,3 +120,8 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID) PCM_CAPABILITIES(Highpass Capture PCM_ID, `S32_LE,S24_LE,S16_LE', 16000, 16000, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) + +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQIIR_COEF') +undefine(`DEF_EQIIR_PRIV') diff --git a/tools/topology/sof/pipe-eq-capture.m4 b/tools/topology/sof/pipe-eq-iir-volume-capture.m4 similarity index 73% rename from tools/topology/sof/pipe-eq-capture.m4 rename to tools/topology/sof/pipe-eq-iir-volume-capture.m4 index d368cbd2d005..23f9c02ba83b 100644 --- a/tools/topology/sof/pipe-eq-capture.m4 +++ b/tools/topology/sof/pipe-eq-iir-volume-capture.m4 @@ -18,14 +18,14 @@ include(`eq_iir.m4') define(`PGA_NAME', Dmic0) define(`CONTROL_NAME_VOLUME', Capture Volume) define(`CONTROL_NAME_SWITCH', Capture Switch) -define(`CONTROL_NAME', `CONTROL_NAME_VOLUME') +define(`CONTROL_NAME', `PIPELINE_ID CONTROL_NAME_VOLUME') # # Controls # # Volume Mixer control with max value of 32 -C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, +C_CONTROLMIXER(Capture Volume, PIPELINE_ID, CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), @@ -35,10 +35,11 @@ C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, Channel register and shift for Front Left/Right, LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) -define(`CONTROL_NAME', `CONTROL_NAME_SWITCH') +undefine(`CONTROL_NAME') +define(`CONTROL_NAME', `PIPELINE_ID CONTROL_NAME_SWITCH') # Switch type Mixer Control with max value of 1 -C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID, +C_CONTROLMIXER(Capture Switch, PIPELINE_ID, CONTROLMIXER_OPS(volsw, 259 binds the mixer control to switch get/put handlers, 259, 259), CONTROLMIXER_MAX(max 1 indicates switch type control, 1), false, @@ -48,17 +49,25 @@ C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID, "1", "1") # Volume Configuration -W_VENDORTUPLES(capture_pga_tokens, sof_volume_tokens, +define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID)) +define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID)) + +W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens, LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"')) -W_DATA(capture_pga_conf, capture_pga_tokens) +W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS) -# Use 50 Hz highpass response with +20 dB gain -include(`eq_iir_coef_highpass_50hz_20db_48khz.m4') +define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID)) +define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID)) + +# By default, use 40 Hz highpass response with +0 dB gain for 48khz +# TODO: need to implement middle level macro handler per pipeline +ifdef(`DMICPROC_FILTER1', , `define(DMICPROC_FILTER1, eq_iir_coef_highpass_40hz_0db_48khz.m4)') +include(DMICPROC_FILTER1) # EQ Bytes control with max value of 255 -C_CONTROLBYTES(EQIIR_C48, PIPELINE_ID, +C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID, CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), @@ -68,7 +77,7 @@ C_CONTROLBYTES(EQIIR_C48, PIPELINE_ID, , , , CONTROLBYTES_MAX(, 304), , - EQIIR_HP50HZ20dB48K_priv) + DEF_EQIIR_PRIV) # # Components and Buffers @@ -80,11 +89,11 @@ W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2) # "Volume" has 2 source and 2 sink periods W_PGA(0, PIPELINE_FORMAT, 2, 2, - capture_pga_conf, LIST(` ', - "CONTROL_NAME_VOLUME", "CONTROL_NAME_SWITCH")) + DEF_PGA_CONF, LIST(` ', + "PIPELINE_ID CONTROL_NAME_VOLUME", "PIPELINE_ID CONTROL_NAME_SWITCH")) # "EQ 0" has 2 sink period and x source periods -W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "EQIIR_C48")) +W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "DEF_EQIIR_COEF")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, @@ -130,3 +139,8 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID) PCM_CAPABILITIES(Highpass Capture PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536) + +undefine(`DEF_PGA_TOKENS') +undefine(`DEF_PGA_CONF') +undefine(`DEF_EQIIR_COEF') +undefine(`DEF_EQIIR_PRIV')