diff --git a/tools/topology/CMakeLists.txt b/tools/topology/CMakeLists.txt index e33af03d5547..24182c94ce6a 100644 --- a/tools/topology/CMakeLists.txt +++ b/tools/topology/CMakeLists.txt @@ -109,6 +109,7 @@ set(TPLGS "sof-tgl-rt711-i2s-rt1308\;sof-tgl-rt711-i2s-rt1308\;-DHDMI=1" "sof-tgl-rt711-i2s-rt1308\;sof-tgl-rt711-i2s-rt1308-nohdmi" "sof-tgl-rt711-rt1308\;sof-tgl-rt711-rt1308" + "sof-tgl-rt5682\;sof-tgl-rt5682\;-DHDMI=1" "sof-tgl-nocodec\;sof-ehl-nocodec" "sof-ehl-rt5660\;sof-ehl-rt5660\;-DHDMI=1" "sof-ehl-rt5660\;sof-ehl-rt5660-nohdmi" diff --git a/tools/topology/sof-tgl-rt5682.m4 b/tools/topology/sof-tgl-rt5682.m4 new file mode 100644 index 000000000000..dcf91d5e96ad --- /dev/null +++ b/tools/topology/sof-tgl-rt5682.m4 @@ -0,0 +1,222 @@ +# +# Topology for Tigerlake with rt5682 headset codec +# + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include Tigerlake DSP configuration +include(`platform/intel/tgl.m4') +include(`platform/intel/dmic.m4') + +DEBUG_START + +# +# Define the pipelines +# +# PCM0 ---> volume ----> ALH 2 BE dailink 0 +# PCM1 <--- volume <---- ALH 3 BE dailink 1 +# PCM3 <----volume <---- DMIC01 +# PCM4 <----volume <---- DMIC16k + +ifelse(HDMI, `1', +` +# PCM5 ----> volume -----> iDisp1 (HDMI/DP playback, BE link 4) +# PCM6 ----> volume -----> iDisp2 (HDMI/DP playback, BE link 5) +# PCM7 ----> volume -----> iDisp3 (HDMI/DP playback, BE link 6) +# PCM8 ----> volume -----> iDisp4 (HDMI/DP playback, BE link 7) +') + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate, +dnl time_domain, sched_comp) + +# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 1, 0, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + +# Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, + 2, 1, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + +# Passthrough capture pipeline 3 on PCM 3 using max 4 channels. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, + 3, 3, 4, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + +# Passthrough capture pipeline 4 on PCM 4 using max 4 channels. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-capture-16khz.m4, + 4, 4, 2, s16le, + 1000, 0, 0, + 16000, 16000, 16000) + +ifelse(HDMI, `1', +` +# Low Latency playback pipeline 5 on PCM 5 using max 2 channels of s32le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 5, 5, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + +# Low Latency playback pipeline 6 on PCM 6 using max 2 channels of s32le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 6, 6, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + +# Low Latency playback pipeline 7 on PCM 7 using max 2 channels of s32le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 7, 7, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + +# Low Latency playback pipeline 8 on PCM 8 using max 2 channels of s32le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 8, 8, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) +') + +# +# DAIs configuration +# + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core, time_domain) + +# playback DAI is ALH(SDW0 PIN2) using 2 periods +# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 1, ALH, 2, SDW0-Playback, + PIPELINE_SOURCE_1, 2, s24le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is ALH(SDW0 PIN2) using 2 periods +# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 2, ALH, 3, SDW0-Capture, + PIPELINE_SINK_2, 2, s24le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# playback DAI is ALH(SDW1 PIN2) using 2 periods +# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0 + +# capture DAI is DMIC01 using 2 periods +# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 3, DMIC, 0, dmic01, + PIPELINE_SINK_3, 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is DMIC16k using 2 periods +# Buffers use s16le format, with 16 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 4, DMIC, 1, dmic16k, + PIPELINE_SINK_4, 2, s16le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +ifelse(HDMI, `1', +` +# playback DAI is iDisp1 using 2 periods +# Buffers use s32le format, 1000us deadline on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 5, HDA, 0, iDisp1, + PIPELINE_SOURCE_5, 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# playback DAI is iDisp2 using 2 periods +# Buffers use s32le format, 1000us deadline on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 6, HDA, 1, iDisp2, + PIPELINE_SOURCE_6, 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# playback DAI is iDisp3 using 2 periods +# Buffers use s32le format, 1000us deadline on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 7, HDA, 2, iDisp3, + PIPELINE_SOURCE_7, 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# playback DAI is iDisp4 using 2 periods +# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 8, HDA, 3, iDisp4, + PIPELINE_SOURCE_8, 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) +') + +# PCM Low Latency, id 0 +dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) + +PCM_PLAYBACK_ADD(SDW-Headphone, 0, PIPELINE_PCM_1) +PCM_CAPTURE_ADD(SDW-Headset_Mic, 1, PIPELINE_PCM_2) +PCM_CAPTURE_ADD(DMIC, 2, PIPELINE_PCM_3) +PCM_CAPTURE_ADD(DMIC16kHz, 3, PIPELINE_PCM_4) + +ifelse(HDMI, `1', +` +PCM_PLAYBACK_ADD(HDMI1, 4, PIPELINE_PCM_5) +PCM_PLAYBACK_ADD(HDMI2, 5, PIPELINE_PCM_6) +PCM_PLAYBACK_ADD(HDMI3, 6, PIPELINE_PCM_7) +PCM_PLAYBACK_ADD(HDMI4, 7, PIPELINE_PCM_8) +') + +# +# BE configurations - overrides config in ACPI if present +# + +#ALH dai index = ((link_id << 8) | PDI id) +#ALH SDW0 Pin2 (ID: 0) +DAI_CONFIG(ALH, 2, 0, SDW0-Playback) + +#ALH SDW0 Pin3 (ID: 1) +DAI_CONFIG(ALH, 3, 1, SDW0-Capture) + +# dmic01 (ID: 2) +DAI_CONFIG(DMIC, 0, 2, dmic01, + DMIC_CONFIG(1, 500000, 4800000, 40, 60, 48000, + DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, + PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1))) + +# dmic16k (ID: 3) +DAI_CONFIG(DMIC, 1, 3, dmic16k, + DMIC_CONFIG(1, 500000, 4800000, 40, 60, 16000, + DMIC_WORD_LENGTH(s16le), 400, DMIC, 1, + PDM_CONFIG(DMIC, 1, STEREO_PDM0))) + +ifelse(HDMI, `1', +` +# 4 HDMI/DP outputs (ID: 4,5,6,7) +DAI_CONFIG(HDA, 0, 4, iDisp1) +DAI_CONFIG(HDA, 1, 5, iDisp2) +DAI_CONFIG(HDA, 2, 6, iDisp3) +DAI_CONFIG(HDA, 3, 7, iDisp4) +') + +DEBUG_END