From 7a1e0b565d56a2a338f8c4432dd8eb2d6aa551b7 Mon Sep 17 00:00:00 2001 From: Libin Yang Date: Fri, 7 Feb 2020 13:41:09 +0800 Subject: [PATCH 1/2] topology: add pipe-volume-switch-capture pipeline This patch adds the capture pipeline which enables the volume and switch controls. In the switch control, it enables capture LED controlling. Signed-off-by: Libin Yang --- .../sof/pipe-volume-switch-capture.m4 | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 tools/topology/sof/pipe-volume-switch-capture.m4 diff --git a/tools/topology/sof/pipe-volume-switch-capture.m4 b/tools/topology/sof/pipe-volume-switch-capture.m4 new file mode 100644 index 000000000000..ddeedc6dcf6e --- /dev/null +++ b/tools/topology/sof/pipe-volume-switch-capture.m4 @@ -0,0 +1,89 @@ +# Passthrough with volume/switch Pipeline and PCM +# +# Pipeline Endpoints for connection are :- +# +# host PCM_C <-- B0 <-- Volume 0 <-- B1 <-- source DAI0 + +# Include topology builder +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`pga.m4') +include(`dai.m4') +include(`mixercontrol.m4') +include(`pipeline.m4') + +# +# Controls +# +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 80), + false, + CONTROLMIXER_TLV(TLV 80 steps from -50dB to +30dB for 1dB, vtlv_m50s1), + Channel register and shift for Front Left/Right, + LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) + +C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 259 binds the mixer control to switch get/put handlers, 259, 259), + CONTROLMIXER_MAX(max 1 indicates switch type control, 1), + false, + , + Channel register and shift for Front Left/Right, + LIST(` ', KCONTROL_CHANNEL(FL, 2, 0), KCONTROL_CHANNEL(FR, 2, 1)), + "1", "1") + +# +# Volume Configuration +# + +W_VENDORTUPLES(capture_pga_tokens, sof_volume_tokens, +LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"' + ` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"')) + +W_DATA(capture_pga_conf, capture_pga_tokens) + +# +# Components and Buffers +# + +# Host "Passthrough Capture" PCM +# with 0 sink and 2 source periods +W_PCM_CAPTURE(PCM_ID, Passthrough Capture, 0, 2) + +# "Volume" has x source and 2 sink periods +W_PGA(0, PIPELINE_FORMAT, 2, DAI_PERIODS, capture_pga_conf, LIST(` ', "PIPELINE_ID Master Capture Volume", "PIPELINE_ID Master Capture Switch")) + +# Capture Buffers +W_BUFFER(0, COMP_BUFFER_SIZE(2, + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), + PLATFORM_HOST_MEM_CAP) +W_BUFFER(1, COMP_BUFFER_SIZE(DAI_PERIODS, + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), + PLATFORM_DAI_MEM_CAP) + +# +# Pipeline Graph +# +# host PCM_P <-- B0 <-- Volume 0 <-- B1 <-- sink DAI0 + +P_GRAPH(pipe-pass-vol-capture-PIPELINE_ID, PIPELINE_ID, + LIST(` ', + `dapm(N_PCMC(PCM_ID), N_BUFFER(0))', + `dapm(N_BUFFER(0), N_PGA(0))', + `dapm(N_PGA(0), N_BUFFER(1))')) + +# +# Pipeline Source and Sinks +# +indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(1)) +indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Capture PCM_ID) + +# +# PCM Configuration +# + +PCM_CAPABILITIES(Passthrough Capture PCM_ID, `S32_LE,S24_LE,S16_LE', + PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS, + 2, 16, 192, 16384, 65536, 65536) From d5ea915829be621f00471f0aba5d97701591c343 Mon Sep 17 00:00:00 2001 From: Libin Yang Date: Tue, 25 Feb 2020 08:52:01 +0800 Subject: [PATCH 2/2] topology: sof-icl-rt711-rt1308-rt715 add MIC MUTE LED support Add support of MIC Mute LED for capture on sof-icl-rt711-rt1308-rt715 platform. Signed-off-by: Libin Yang --- tools/topology/sof-icl-rt711-rt1308-rt715-hdmi.m4 | 4 ++-- tools/topology/sof-icl-rt711-rt1308-rt715.m4 | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/topology/sof-icl-rt711-rt1308-rt715-hdmi.m4 b/tools/topology/sof-icl-rt711-rt1308-rt715-hdmi.m4 index 671270f69720..0ab6bfd1c3a8 100644 --- a/tools/topology/sof-icl-rt711-rt1308-rt715-hdmi.m4 +++ b/tools/topology/sof-icl-rt711-rt1308-rt715-hdmi.m4 @@ -49,7 +49,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, # Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le. # Schedule 48 frames per 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, 2, 1, 2, s32le, 1000, 0, 0, 48000, 48000, 48000) @@ -71,7 +71,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, # Low Latency capture pipeline 5 on PCM 4 using max 2 channels of s32le. # Schedule 48 frames per 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, 5, 4, 2, s32le, 1000, 0, 0, 48000, 48000, 48000) diff --git a/tools/topology/sof-icl-rt711-rt1308-rt715.m4 b/tools/topology/sof-icl-rt711-rt1308-rt715.m4 index 6861e610902f..9781644debd2 100644 --- a/tools/topology/sof-icl-rt711-rt1308-rt715.m4 +++ b/tools/topology/sof-icl-rt711-rt1308-rt715.m4 @@ -42,7 +42,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, # Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le. # Schedule 48 frames per 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, 2, 1, 2, s32le, 1000, 0, 0, 48000, 48000, 48000) @@ -63,7 +63,7 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, # Low Latency capture pipeline 5 on PCM 4 using max 2 channels of s32le. # Schedule 48 frames per 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, +PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, 5, 4, 2, s32le, 1000, 0, 0, 48000, 48000, 48000)