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[BUG] cavs: icl: core 3 must be powered on startup by the driver #2434
Describe the bug
Since the DSP starts at full throttle (HP-RO 400 MHz is used as a clock source), the driver should set SPA for core3 in addition to core0 in order to propagate required notifications to other units. This should be done "silently", run-time environment for core3 is not required at this point, so the FW does not need to know about this.
In future, when more power optimizations will be implemented for icl, the FW will notify the driver (some new pwr state changed notification) when switching to LP-RO 120 MHz and back and the driver may toggle core3 SPA accordingly.
changed the title [-][WIP] [BUG] cavs: core 3 must be powered on for loads > 120 MCPS on icl[/-][+][BUG] cavs: icl: core 3 must be powered on startup by the driver[/+]on Aug 22, 2019
@lgirdwood I dont think we've tried it yet. I think Pierre asked for more details but @mmaka1 hasnt replied yet.
At the moment the code loading sequence powers up all 4 cores before loading the FW. Not sure what Marcin means here and when Core 3 should be powered up precisely.
@ranj063 I'll get back to you once SW/FW programming sequence is finalized for scenarios that require HP Ring Oscillator (400 MHz) clock. Could you confirm current implementation in the driver for initial boot:
Set SPA(0..PLATFORM_CORE_COUNT) bit
Wait for CPA (0..PLATFORM_CORE_COUNT) bit
Wait for FW ready
SPA is not set to 0 for cores (1..PLATFORM_CORE_COUNT) -> all cores are up ?
Activity
plbossart commentedon Aug 22, 2019
@mmaka1 care to provide more details? We see random IPC and underflows on ICL w/ SoundWire, if there is a connection.
[-][WIP] [BUG] cavs: core 3 must be powered on for loads > 120 MCPS on icl[/-][+][BUG] cavs: icl: core 3 must be powered on startup by the driver[/+]lgirdwood commentedon Aug 30, 2019
@plbossart @ranj063 has anyone tried this yet ?
ranj063 commentedon Aug 30, 2019
@lgirdwood I dont think we've tried it yet. I think Pierre asked for more details but @mmaka1 hasnt replied yet.
At the moment the code loading sequence powers up all 4 cores before loading the FW. Not sure what Marcin means here and when Core 3 should be powered up precisely.
lbetlej commentedon Jan 7, 2020
@ranj063 I'll get back to you once SW/FW programming sequence is finalized for scenarios that require HP Ring Oscillator (400 MHz) clock. Could you confirm current implementation in the driver for initial boot:
tlauda commentedon Apr 29, 2020
@lbetlej Should we move this to linux repo, since it looks like additional work for kernel?
plbossart commentedon Sep 15, 2020
I don't understand what the issue is and what in the driver code should be modified. As @ranj063 mentioned it all 4 cores get powered.
mengdonglin commentedon Sep 21, 2020
@ranj063 @fredoh9 Can we close this issue now if all 4 cores get powered? Or need we wait for ICCMAX implementation on ICL is done on ICL?
fredoh9 commentedon Sep 25, 2020
There was some fixes required in SOF firmware. First one is thesofproject/sof#3465,
I got a patch today. Will continue to work on this.
thesofproject/sof#3473
fredoh9 commentedon Sep 28, 2020
Without https://github.com/thesofproject/sof/pull/2957/files, there is no extended manifest support. This is not SOF v1.6 blocker.
fredoh9 commentedon Nov 16, 2020
#2548 merged