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pinctrl: tigerlake: Use generic flag for special GPIO base treatment
Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
1 parent cf2f2c3 commit d4b41f8

1 file changed

Lines changed: 15 additions & 17 deletions

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‎drivers/pinctrl/intel/pinctrl-tigerlake.c‎

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,6 @@
2121
#define TGL_GPI_IS 0x100
2222
#define TGL_GPI_IE 0x120
2323

24-
#define TGL_NO_GPIO -1
25-
2624
#define TGL_GPP(r, s, e, g) \
2725
{ \
2826
.reg_num = (r), \
@@ -342,30 +340,30 @@ static const struct pinctrl_pin_desc tgllp_pins[] = {
342340
};
343341

344342
static const struct intel_padgroup tgllp_community0_gpps[] = {
345-
TGL_GPP(0, 0, 25, 0), /* GPP_B */
346-
TGL_GPP(1, 26, 41, 32), /* GPP_T */
347-
TGL_GPP(2, 42, 66, 64), /* GPP_A */
343+
TGL_GPP(0, 0, 25, 0), /* GPP_B */
344+
TGL_GPP(1, 26, 41, 32), /* GPP_T */
345+
TGL_GPP(2, 42, 66, 64), /* GPP_A */
348346
};
349347

350348
static const struct intel_padgroup tgllp_community1_gpps[] = {
351-
TGL_GPP(0, 67, 74, 96), /* GPP_S */
352-
TGL_GPP(1, 75, 98, 128), /* GPP_H */
353-
TGL_GPP(2, 99, 119, 160), /* GPP_D */
354-
TGL_GPP(3, 120, 143, 192), /* GPP_U */
355-
TGL_GPP(4, 144, 170, 224), /* vGPIO */
349+
TGL_GPP(0, 67, 74, 96), /* GPP_S */
350+
TGL_GPP(1, 75, 98, 128), /* GPP_H */
351+
TGL_GPP(2, 99, 119, 160), /* GPP_D */
352+
TGL_GPP(3, 120, 143, 192), /* GPP_U */
353+
TGL_GPP(4, 144, 170, 224), /* vGPIO */
356354
};
357355

358356
static const struct intel_padgroup tgllp_community4_gpps[] = {
359-
TGL_GPP(0, 171, 194, 256), /* GPP_C */
360-
TGL_GPP(1, 195, 219, 288), /* GPP_F */
361-
TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */
362-
TGL_GPP(3, 226, 250, 320), /* GPP_E */
363-
TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */
357+
TGL_GPP(0, 171, 194, 256), /* GPP_C */
358+
TGL_GPP(1, 195, 219, 288), /* GPP_F */
359+
TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
360+
TGL_GPP(3, 226, 250, 320), /* GPP_E */
361+
TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
364362
};
365363

366364
static const struct intel_padgroup tgllp_community5_gpps[] = {
367-
TGL_GPP(0, 260, 267, 352), /* GPP_R */
368-
TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */
365+
TGL_GPP(0, 260, 267, 352), /* GPP_R */
366+
TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */
369367
};
370368

371369
static const struct intel_community tgllp_communities[] = {

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